Multi-level collaborative low-power design method

A design method, low-power technology, applied in computing, special data processing applications, data processing power supply, etc., can solve problems such as stability and performance degradation, affecting processor stability, processor restriction and impact, etc., to achieve dynamic Power consumption reduction, optimization of good power consumption, effect of avoiding invalid flips

Active Publication Date: 2013-11-27
BEIHANG UNIV
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AI Technical Summary

Problems solved by technology

Generally speaking, the low-power design of processors faces the following challenges: First, dynamic power consumption and voltage have a quadratic relationship, and voltage reduction can significantly reduce dynamic power consumption, resulting in a continuous reduction in power supply voltage. However, due to the reduction in voltage, leakage Dramatic increase in power consumption and significant drop in stability and performance
Secondly, with the emergence of multi-core technology, although the acceleration of power consumption density has been greatly reduced, the increase in overall power consumption is still a problem that cannot be ignored.
[0003] Power consumption is one of the most basic electrical performance indicators of processor performance. One of the very important reasons is that with the increase of frequency, the increase of power consumption is accompanied by the change of thermal characteristics. Can have serious constraints and impacts; increased power consumption can also affect processor stability

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Embodiment Construction

[0041] The core part of the present invention is as Figure 4 As shown, this part needs to complete the multi-level low-power co-optimization functions of system level, register transfer level and gate level. The overall structure mainly includes four parts, JTAG module, programmable interrupt controller (PIC) module, power management module (power management) module and gated clock module. The gated clock module mainly includes two sub-modules, namely the gated clock module controlling the processor (cpu) and the gated clock module controlling the tick timer (Tick Timer).

[0042] In the specific implementation process, we need to test all modules to ensure that all modules can work normally, and debug them as a whole to ensure that their online debugging interface with the host computer is normal and their functions are normal. Collaborative low-power design at different levels, low-power design for the system level, register transfer level and gate level respectively to re...

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Abstract

A multi-level collaborative low-power design method includes firstly establishing an SoC (system on chip); secondly, completing a system-level low-power design; thirdly, completing a register transfer-level low-power design; fourthly, completing a gate-level low-power design; and fifthly, completing system function verification. The design method is operated from the top to the bottom, results of power optimization of each level are overlapped, the low-power design is performed at multiple levels collaboratively, and optimization and choosing of power can be performed better as required; the power of the entire system is lowered, meanwhile, normal functions can be guaranteed, and effect of lowering the power is more significant.

Description

technical field [0001] The invention relates to a multi-level collaborative low-power design method, which is a method for reducing system dynamic power consumption for on-chip system hardware circuits, and belongs to the technical field of integrated circuit low-power design. The invention can especially be used for low power consumption design of the system on chip at system level, register transmission level and gate level, so that the dynamic power consumption of the system becomes lower. Background technique [0002] In recent years, with the emergence of a large number of portable devices in the embedded field, coupled with the current situation of energy shortage and environmental protection, the problem of processor power consumption has received more and more attention, especially since entering this century, low power consumption It has become an important indicator of embedded processors and even every electronic device. Generally speaking, the low-power design o...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F1/32
Inventor 王翔张溢
Owner BEIHANG UNIV
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