A Serial Cascaded Single-bit Filter Structure for Eliminating Glitch Signals

Abstract

The invention relates to a serially cascaded single-bit filter structure for eliminating spur signals, comprising: a serially cascaded single-bit filter module, a loop counter circuit, a metastable elimination circuit; a serially cascaded single-bit filter module The filter module further includes a first-level single-bit filtering module, a second-level single-bit filtering module, a third-level single-bit filtering module... an nth-level single-bit filtering module; The original data disturbed by the glitch signal is recovered from each sampled data, and the design of eliminating glitch signals of different widths is realized by cascading single-bit filters in series, and the pulse signals of different sampling clock widths are filtered out step by step; The traditional equal time interval sampling scheme cannot correctly restore the insufficiency of the equal time interval glitch signal, and a general glitch signal elimination circuit is realized.

Description

technical field [0001] The invention relates to a serial cascaded single-bit filter structure for eliminating burr signals, and belongs to the technical field of signal processing. Background technique [0002] With the increase of the signal speed of the circuit system and the deterioration of the electromagnetic environment, when the length of the transmission cable used is relatively long, crosstalk will occur between the transmitted signals, resulting in glitch signals; there are also different degrees of crosstalk between signals inside the PCB board. Glitch signals are generated; due to competition risks inside the chip, glitch signals are generated; glitch signals on different occasions have different impacts on the system, but they all lead to system instability or potential risks. [0003] At present, the processing of burr elimination on the input signal mainly uses equal interval time sampling, but there are obvious shortcomings in such processing: [0004] 1. Fo...

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Problems solved by technology

[0004] 1. For a glitch signal whose width is less than one sampling clock period, when the phase of the glitch signal and the sampling clock changes, the glitch signal will be randomly sampled, or the glitch signal will not be sampled, and the randomness will affect the system. System problems may not necessarily Recurrence, serious impact on system stability

[0005] 2. For two consecutive glitch signals, if the two glitch signals are sampled by two consecutive sampling clocks, it will produce the illusion of continuously receiving the effective level of the width of two sampling clocks, and the real signal is difficult to recover

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