Serial cascade single-bit filter structure for eliminating burr signals

Abstract

The invention discloses a serial cascade single-bit filter structure for eliminating burr signals. The serial cascade single-bit filter structure comprises a serial single-bit filter module, a cycle counter circuit and a metastable state cancelling circuit; the serial single-bit filter module comprises a first single-bit filter module, a second single-bit filter module, a third single-bit filter module...n single-bit filter module. Primary data interfered by the burr signals can be restored according to two adjacent sampling data by the single-bit filter, the design of eliminating the burr signals of different widths can be limited by the way of the serial cascade single-bit filter, and the pulse signals of different sampling clock widths can be gradually filtrated; furthermore, the defects that the equitime interval burr signals cannot be correctly restored by a traditional equitime interval sampling project can be prevented, and a universal burr signal cancelling circuit can be realized.

Description

technical field [0001] The invention relates to a serial cascaded single-bit filter structure for eliminating burr signals, and belongs to the technical field of signal processing. Background technique [0002] With the increase of the signal speed of the circuit system and the deterioration of the electromagnetic environment, when the length of the transmission cable used is relatively long, crosstalk will occur between the transmitted signals, resulting in glitch signals; there are also different degrees of crosstalk between signals inside the PCB board. Glitch signals are generated; due to competition risks inside the chip, glitch signals are generated; glitch signals on different occasions have different impacts on the system, but they all lead to system instability or potential risks. [0003] At present, the burr removal processing of the input signal mainly uses equal interval time sampling, but there are obvious shortcomings in this processing: [0004] 1. For a gli...

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Problems solved by technology

[0004] 1. For a glitch signal whose width is less than one sampling clock period, when the phase of the glitch signal and the sampling clock changes, the glitch signal will be randomly sampled, or the glitch signal will not be sampled, and the randomness will affect the system. System problems may not necessarily Recurrence, serious impact on system stability

[0005] 2. For two consecutive glitch signals, if the two glitch signals are sampled by two consecutive sampling clocks, it will produce the illusion of continuously receiving the effective level of the width of two sampling clocks, and the real signal is difficult to recover

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