Multiphase clock transfer circuit and method

Abstract

A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

Description

technical field [0001] The present invention relates to clock transfer technology in semiconductor integrated circuits. Background technique: [0002] In a semiconductor integrated circuit, a plurality of clocks having the same frequency and maintaining a predetermined phase difference can be used. Such multiple clocks are called polyphase clocks. When a multiphase clock is used, conventionally, a clock generation circuit configured with a PLL (phase locked loop: phase locked loop) or the like generates and outputs a multiphase clock. Then, the multi-phase clocks are distributed to the required circuit unit blocks through the dedicated wiring for transmitting the respective phase clocks. An example of such a technique is disclosed in JP-A-2-255908. [0003] However, if the multi-phase clock is transmitted by the conventional method, in order to transmit the clock of each phase separately, when transmitting the clock of M phases (m is a natural number), m wires are require...

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Problems solved by technology

[0003] However, if the multi-phase clock is transmitted by the conventional method, in order to transmit the clock of each phase separately, when transmitting the clock of M phases (m is a natural number), m wires are required. As m becomes larger, the wiring area increases accordingly.

[0004] In addition, if the distance to transmit the clock is long, in general, the difference in the route length between the clocks of each phase will increase, and the influence of interference with other signal lines will also increase. The skew between the clocks will increase

[0005] Also, if the frequency of the clock is high, the ratio of the asymmetry between the clocks of the transmitted phases to the clock period will increase

For this reason, the phase relationship between the clocks of each phase cannot be guaranteed in each circuit unit block receiving multi-phase clocks, resulting in erroneous operation of the circuit

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