1696results about "Printed capacitor incorporation" patented technology

A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Disclosed are appendage mountable electronic systems and related methods for covering and conforming to an appendage surface. A flexible or stretchable substrate has an inner surface for receiving an appendage, including an appendage having a curved surface, and an opposed outer surface that is accessible to external surfaces. A stretchable or flexible electronic device is supported by the substrate inner and/or outer surface, depending on the application of interest. The electronic device in combination with the substrate provides a net bending stiffness to facilitate conformal contact between the inner surface and a surface of the appendage provided within the enclosure. In an aspect, the system is capable of surface flipping without adversely impacting electronic device functionality, such as electronic devices comprising arrays of sensors, actuators, or both sensors and actuators.

Apparatus for suppressing noise and electromagnetic coupling in the printed circuit board of an electronic device includes an upper conductive plate and an array of conductive coplanar patches positioned a distance t₂ from the upper conductive plate. The distance t₂ is chosen to optimize capacitance between the conductive coplanar patches and the upper conductive plate for suppression of noise or electromagnetic coupling. The apparatus further includes a lower conductive plate a distance t₁ from the array of conductive coplanar patches and conductive rods extending from respective patches to the lower conductive plate.

A detonator assembly is provided for use in oilfield operations to detonate an explosive downhole including a capacitor discharge unit and initiator electrically connected together to form a single unit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

The invention provides electronic parts which comprise a composite dielectric layer composed of an organic insulating material and a dielectric ceramic powder having a larger relative dielectric constant than the organic insulating material, and which also comprise conductive element sections forming inductor elements, etc., wherein the organic insulating material comprises a cured resin obtained by curing reaction of an epoxy resin with an active ester compound obtained by reaction between a compound with two or more carboxyl groups and a compound with a phenolic hydroxyl group. The dielectric ceramic powders of the described electronic parts have larger relative dielectric constants than the organic insulating materials, and the organic insulating materials have low dielectric loss tangents. It is possible to adequately reduce time-dependent dielectric constant changes in the high-frequency range of 100 MHz and above even with prolonged use at high temperatures of 100° C. and higher, while it is also possible to satisfactorily prevent deformation and other damage to the electronic parts during their handling.

A signal transmission structure includes a driving circuit block, a receiving circuit block, a main transmission line, and a copper patch. The main transmission line connects the driving circuit block to the receiving circuit block for transmitting signals therebetween. The copper patch is arranged at the main transmission line, and has a rectangular shape. The copper patch can reduce switching rates when the signal state of the driving circuit changes rapidly. The copper patch serves as a compensation capacitor, to reduce a rate of switching of the signal, and to reduce or even eliminate the problems of crosstalk and overshooting and undershooting of signals. It is of advantage that the copper patch is simple to manufacture and very suitable for mass production.

An apparatus for suppressing noise in an electronic device includes a multiple layer structure in which localized arrays of chip capacitors and/or patches around sources of electromagnetic waves are used. The PCB includes multiple conductive layers at different potentials, dielectric layers separating the conductive layers, conductive rods extending between at least two of the conductive layers, and a layer of patches disposed adjacent or on one or more of the conductive layers. The conductive rods are connected to one of the conductive layers and chip capacitors connect the conductive rods to another of the conductive layers. A particular location can be effectively isolated from noise using a few unit cells of an array of patches/capacitors partially or completely surrounding the particular location.

An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Methods are disclosed for printing (2-7) multilayer electronic components, and circuits on a surface (2), where at least one of the layers is formed by a redox reaction (6) occurring in a deposited solution (4, 5). Electronic components may comprise semiconductors such as in transistors or diode, or metal oxide or electrolyte such as in batteries or fuel cells, or are capacitors, inductors, and resistors. Preferably, the oxidizer of the redox reaction is a strong oxidizer, and the reducer is a strong reducer (3). Reactions are preferably sufficiently exothermic that they can be initiated (6), rather than driven to completion, by microwave or other suitable energy sources, and may yield substantially pure metal or metal oxide layers. The solution being deposited (5) may have either high concentrations of particulates, such as 60-80 wt. % of dry weight, or low concentrations of particulates, such as ≦5 wt. % or ≦2 wt. %. Low particulate content provides printing of structures having lateral resolution of ≦10 μm, ≦5 μm, or ≦1 μm.

A insulation displacement connector (IDC) patch panel includes a circuit (PC) board with interdigitated capacitance for balancing out inherent capacitance found within IDCs of the panel and conventional plug connectors coupled to the panel. Unwanted cross-talk signals are reduced as a consequence.

The present invention relates to RJ45 modular inserts that are connected to a printed circuit board used to transfer high speed signals for telecommunication interface media connections. The printed circuit board is configured to reduce near-end cross-talk (“NEXT”) without compromising impedance. NEXT is substantially reduced by utilizing a low reactance dielectric insert with a two-stage combination positive and negative compensation removal technique. By utilizing this method, the pair-to-pair NEXT is substantially reduced and differential pair impedance are controlled in a simple and cost effective manner.

The present invention comprises methods for making three-dimensional (3-D) liquid crystalline polymer (LCP) interconnect structures using a high temperature singe sided liquid crystalline polymer, and low temperature single sided liquid crystalline polymer, whereas both the high temperature LCP and the low temperature LCP are drilled using a laser or mechanical drill or mechanically punch to form a z-axis connection. The single sided Conductive layer is used as a bus layer to form z axis conductive stud conductive stud within the high temperature and low temperature LCP, followed by deposition of a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis electrical connection. High temperature and low temperature LCP circuit layers are etched or built up to form circuit patterns and subsequently bonded together to form final 3-D multilayer circuit pattern whereas the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas, metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer. The resultant structure is then packaged using two metallized organic cores that are laminated onto either side of the device using a low temperature adhesive with similar electrical properties and subsequently metallized to form the input output terminals and EM shielding.

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer.