42results about How to "Reduce Impedance Discontinuities" patented technology

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer.

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

An interconnection structure for interconnecting circuitry on a first conductive layer to circuitry on a second conductive layer is provided. The interconnection structure of the present invention comprises a signal conductor via surrounded by a plurality of ground vias. The plurality of ground vias shield the signal conductor via, thus providing electrical isolation for the conductor via from the rest of the circuitry. One feature of the present invention is that the plurality of ground vias can be modified, adjusting their diameters and their placement relative to the signal conductor via, in order to affect the overall characteristic impedance of the interconnection structure. This feature is useful when propagating high frequency signals between signal traces on different conductive layers of a printed circuit board. In view of the high frequencies used in today's wireless communication systems, the interconnection structure proposed aids in the practical implementation of radio frequency modules by mitigating the effects of impedance discontinuities ordinarily present at signal trace-to-via transition regions.

A high speed, high reliability connector that may be employed with standard Serial ATA (SATA) or Serial Attached SCSI (SAS) compliant receptacle connectors. The present invention reduces impedance discontinuity by reducing the interconnection length and cross-planar transit found in typical SATA and SAS compliant connectors.

A connector with controlled impedance includes at least one set of differential signal terminals with an associated ground terminal. The ground terminal has a symmetric configuration, while the two differential signal terminals have asymmetric configurations. The asymmetric configurations permit capacitive coupling to occur primarily between the two differential signals in an area of the connector where the inductance of the connector would be high. The two differential signal terminals flank the ground terminal.

The invention relates to the technical field of optical communication, and provides a light emitting assembly. The light emitting assembly comprises an LD chip component, an optical wavelength division multiplexer, a first packaging shell and a second packaging shell; the first packaging shell is fixedly connected with the second packaging shell, so as to form a first cavity for packaging the LD chip component and a second cavity for packaging the optical wavelength division multiplexer; the first cavity is located in the first packaging shell; and the second cavity is located in the second packaging shell. The invention further provides a light module. The light module comprises a shell, and further comprises a light receiving assembly and the light emitting assembly; and the light receiving assembly and the light emitting assembly are both arranged on the shell. The LD chip component and the optical wavelength division multiplexer are separated by adopting a two-section structure, and the processing of light signals is carried out in two steps, so that the yield is improved, and the implementation of the installation process is facilitated; and through the adoption of an opticalfiber adapter set, the assembly tolerance can be effectively compensated by utilizing the flexibility of optical fibers, the stress is eliminated, and the problem of light loss of the assembly due tothe stress is avoided.

A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

A transmission line includes a transmission line substrate, a signal line, and a first ground pattern that is provided on the transmission line substrate and is located between the transmission line substrate and a metal wire used to connect the signal line to a component.

The invention discloses a multi-layer circuit structure which includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones. The conductive pattern is electrically connected to a reference potential and electrically insulated from the differential transmission line pair.

The invention discloses an optical module and communication equipment. The optical module comprises a substrate, an electric chip, a high-speed signal line and a capacitor. The electric chip, the high-speed signal line and the capacitor are arranged on the substrate. The capacitor is connected between the electric chip and the high-speed signal line. The capacitor comprises a first pole plate anda second pole plate. The first pole plate is connected with a corresponding bonding pad of the electric chip through a signal bonding line, and the second pole plate is connected with the high-speed signal line. The mode in which the electric chip is directly connected to the capacitor through the bonding line and the capacitor is then connected to the high-speed signal line instead of the mode inwhich the electric chip is connected to the high-speed signal line through the bonding line and the capacitor is arranged in the middle section of the path of the high-speed signal line is adopted. Therefore, the number of impedance discontinuity points on a high-speed signal transmission path is reduced, and the integrity of a high-speed signal is improved.

The invention provides an optical module comprising a circuit board, a light emitting sub-module and a flexible circuit board; the light emitting sub-module comprises a shell and a ceramic switching block plated with a metal layer, one side of the ceramic switching block is inserted into the shell, and the other side of the ceramic switching block is exposed outside the shell; signal and grounding bonding pads are arranged on the metal layer of the ceramic switching block, and the signal bonding pads on the inner side and the outer side of the ceramic switching block are connected; an isolation groove is formed between the signal bonding pad and the grounding bonding pad located on the outer side of the shell and on the ceramic switching block, and the isolation groove is sunken in the signal bonding pad and the grounding bonding pad; and one end of the flexible circuit board is connected with the ceramic switching block, and the other end of the flexible circuit board is connected with the circuit board. The isolation groove is formed between the signal bonding pad and the grounding bonding pad, exposed on the outer side of the shell, on the ceramic switching block, the isolation groove is sunken in the signal bonding pad, the dielectric constant of the ceramic switching block is reduced through the isolation groove, impedance discontinuous points at the connecting position of the flexible circuit board and the ceramic switching block are reduced, and thus the signal transmission quality is improved, and the signal integrity is ensured.

Provided is a structure for reducing an impedance-discontinuity in a flexible printed circuit of a hard disk drive. The structure includes an actuator arm, a bracket, a flexible printed circuit having one end installed at the actuator arm and an other end installed at the bracket and including various circuits, and a metal member facing the flexible printed circuit and having one end installed at the actuator arm and an other end installed at the bracket.

A method and apparatus are provided for reducing impedance discontinuities which occur when two expansion connectors are located very close to one another on a bus in an information handling system. An interconnect is situated between the two expansion connectors and exhibits an impedance which is selected to be sufficiently low to compensate for the amount by which the impedance of the expansion bus connectors exceeds the impedance of the expansion bus connected thereto.

A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a user defined delta value. If the compared areas differ greater than the user defined delta value, then a coordinate change is computed for moving the signal wire to reduce characteristic impedance discontinuity.