73results about How to "Sufficient capacitance" patented technology

A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

The energy content of supercapacitor is determined by its capacitance value and working voltage. To attain a high capacitance and a high voltage, several pieces of electrodes and separators are spirally wound with edge sealing to form a bipolar supercapacitor in cylindrical, oval or square configuration. While the winding operation effectively provides a large surface area for high capacitance, the bipolar packaging instantly imparts a unitary roll a minimum working voltage of 5V on using an organic electrolyte. The bipolar roll is a powerful building block for facilitating the assembly of supercapacitor modules. Using containers with multiple compartments, as many bipolar rolls can be connected in series, in parallel or in a combination of the two connections to fabricate integrated supercapacitors with high energy density as required by applications.

A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.

A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor workpiece, an overhead electrode overlying said workpiece support, the electrode comprising a portion of said chamber wall, an RF power generator for supplying power at a frequency of said generator to said overhead electrode and capable of maintaining a plasma within said chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that said overhead electrode and the plasma formed in said chamber at said desired plasma ion density resonate together at an electrode-plasma resonant frequency, said frequency of said generator being at least near said electrode-plasma resonant frequency. The reactor further includes an insulating layer formed on a surface of said overhead electrode facing said workpiece support, a capacitive insulating layer between said RF power generator and said overhead electrode, and a metal foam layer overlying and contacting a surface of said overhead electrode that faces away from said workpiece support.

A pressure sensor (30) for harsh environments such as vehicle tires, formed from a chamber (58) partially defined by a flexible membrane (50), the chamber (58) containing a fluid at a reference pressure. In use, the flexible membrane (50) deflects due to pressure differentials between the reference pressure and the fluid pressure, the membrane being at least partially formed from conductive material. A conductive layer (36) is deposited within the chamber (58) spaced from the flexible membrane (50) such that they form opposing electrodes of a capacitor. Associated circuitry (34) is also deposited for converting the deflection of the flexible membrane (50) into an output signal indicative of the fluid pressure. The conductive layer (36) is less than 50 microns from the membrane in its undeflected state because capacitative sensors with closely spaced electrodes can have small surface area electrodes while maintaining enough capacitance for the required operating range. Furthermore, small electrodes reduce the power consumption of the sensor which in turn reduces the battery size needed for the operational life of the sensor.

The present invention is directed to a conductive electrolyte for use in high voltage electrolytic capacitors and to an electrolytic capacitor impregnated with the electrolyte of the present invention for use in an implantable cardioverter defibrillator (ICD). The electrolyte according to the present invention is composed of a two solvent mixture of ethylene glycol and di(ethylene glycol); a combination of boric acid with an aliphatic dicarboxylic acid of carbon chain length from eight to thirteen, such as suberic, azelaic, sebacic, undecanedioic, dodecanedioic, or brassylic acid; a very long chain dicarboxylic acid, where the acid moieties are separated by 34 carbons; and a nitro-substituted aromatic compound as a degassing agent, such as 3-nitroacetophenone or 2-nitroanisole. This electrolyte is then titrated with a light amine such as ammonia, diethylamine, dimethylamine, trimethylamine, or triethylamine. The electrolyte according to the present invention, when impregnated in an electrolytic capacitor, provides an acceptable breakdown voltage while having a reasonable bulk conductivity. This electrolyte, when impregnated within a capacitor constructed of appropriate foils and paper spacers, should provide a part with a working voltage of at least 500 volts, while having a bulk conductivity of approximately 3 mS / cm.

A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

An antenna apparatus includes: a circuit board that has a main surface and a rear surface opposite to each other; an antenna element that is formed of a metal plate and is arranged at a predetermined distance from the main surface of the circuit board; a plurality of legs that extend from the antenna element toward the circuit board; a ground conductor that is formed on the main surface or the rear surface of the circuit board; a feeding pin that supplies power from the circuit board to the antenna element; and a plurality of comb-shaped capacitor patterns that are formed on one of or both the main surface and the rear surface of the circuit board and are electrically connected between the plurality of legs and the ground conductor.

A plurality of capacitors employing holding layer patterns, and a method of fabricating the same, the plurality of capacitors including a plurality of cylinder-shaped lower plates repeatedly aligned in two dimensions. Holding layer patterns are located between the uppermost portions and the lowermost portions of the plurality of lower plates, and connect the adjacent side walls of the plurality of lower plates. An upper plate fills the spaces inside the plurality of lower plates and the spaces between the side walls of the plurality of lower plates. A capacitor dielectric layer is interposed between the plurality of lower plates and the upper plate, and insulates the lower plates and the upper plate.

A method for forming a capacitor of a semiconductor device which provides improved reliability and characteristics of semiconductor device by removing oxygen from the Ru film using NH3 gas during the deposition process of the Ru film used as storage electrode material or, in the alternative, performing a NH3 plasma treatment after the deposition process of Ru film to inhibit formation of oxide film at the interface of Ru film and barrier metal layer, and then by forming rugged surface on the Ru film with RTP under N2 or NH3 gas atmosphere to obtain a high capacitance for high integration of semiconductor device.

An organic light emitting display device may have a pixel region and a transparent region, and may include a substrate, at least one semiconductor device disposed on the substrate in the pixel region, an organic light emitting structure disposed on the at least one semiconductor device, and a capacitor disposed on the substrate in the transparent region. The capacitor may have a sufficient capacitance without substantially reducing a transmittance of the organic light emitting display device. Additionally, the transparent region of the organic light emitting display device may serve as a mirror in accordance with the material included in a lower electrode of the capacitor and / or an upper electrode of the capacitor.

A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.

A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of second metal element; a second paraelectric film disposed between the first electrode and the first paraelectric film; and a third paraelectric film disposed between the second electrode and the first paraelectric film, wherein the second paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element, and the third paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element.

A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.

A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.

A plurality of capacitors employing holding layer patterns, and a method of fabricating the same, the plurality of capacitors including a plurality of cylinder-shaped lower plates repeatedly aligned in two dimensions. Holding layer patterns are located between the uppermost portions and the lowermost portions of the plurality of lower plates, and connect the adjacent side walls of the plurality of lower plates. An upper plate fills the spaces inside the plurality of lower plates and the spaces between the side walls of the plurality of lower plates. A capacitor dielectric layer is interposed between the plurality of lower plates and the upper plate, and insulates the lower plates and the upper plate.

In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode; and a longitudinal insulated gate static induction transistor in which the other side of the silicon pillar is used as an active region (a source region, a channel formation region and a drain region), and a bit line is connected to the silicon pillar.

A semitransmissive liquid crystal display panel 10 has a first substrate 11 having, formed in each of the areas demarcated by signal lines and scan lines laid in a grid-like shape thereon, a reflective portion and a transmissive portion formed by a pixel electrode 15 having a slit 17, a second substrate 19 having formed thereon a color filter 21, a common electrode 22, and ridges 23 and 41, alignment films 24 laid over the first and second substrates 11 and 19 and processed for vertical alignment, and a liquid crystal layer 25 laid between the first and second substrates 11 and 19 and showing a negative dielectric constant anisotropy. When no electric field is applied to the liquid crystal layer 25, the liquid crystal molecules are vertically aligned, and, when an electric field is applied to the liquid crystal layer 25, the liquid crystal molecules are horizontally aligned and inclined in the directions restricted by the slit 17 and the ridges 23 and 41. The slit 17 is formed in a central portion of the pixel electrode in the transmissive portion, and the ridges 23 and 41 are formed at the periphery of the pixel electrode 15 and in a central portion of the reflective portion.

A liquid crystal device have an element substrate including a scanning line, a data line and a pixel electrode, a cutout is formed on the pixel electrode. A capacitor line for providing a storage capacitor is formed on the element substrate. The capacitor line has a first and second portions. The first portion extends along with the scanning line, and a second line portion overlaps the cutout of the pixel electrode.

A vertical dipole-style antenna operable over a wide range of predetermined frequencies that is made up of two collinear dipole antennas fed either in parallel through a single input connector or individually through two input connectors, contained within the same enclosure, where one dipole covers the VHF portion of the band from 30 MHz to 115 MHz and the other dipole covers the remainder of the band from 115 MHz to 512 MHz and together the two dipoles cover the very wide frequency band of 30 to 512 MHz through a single input connector. The VHF dipole is comprised of an existing vehicular dipole antenna design, while the UHF dipole antenna is comprised of radiating elements fed with a specially design coaxial transformer feedline with wide-band capacitive elements coupling the radiating elements to ground, providing variable loading to control the electrical length of the antenna.

A diesel particulate filter (“DPF”) including vertically and horizontally stacked cells in which all of vertical and horizontal sides are surrounded by walls formed of a porous material, and sealing end faces of the cells alternately vertically and horizontally are provided with first and second electrodes. In a particulate matter (“PM”) sensor in which a PM deposit quantity of the DPF is detected by a capacitance of a capacitor formed by the first and second electrodes, among open cells, the first electrodes are inserted into the open cells arranged in a line in a diagonal direction, and the second electrodes are inserted into the open cells arranged in a line in the diagonal direction and including the open cells secondarily adjacent to each of the open cells into which the first electrodes are inserted.

Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

A plurality of pixel circuits provided in a display apparatus respectively include light-emitting elements OLED, first transistors that supply driving currents to the light-emitting elements, second transistors that turn on and off connection between data lines and gates of the first transistors, and third transistors. The display apparatus has first holding capacitors that are respectively inserted and connected midway on the plurality of data lines and shift levels of driving voltages of the first transistors, and holding capacitors that respectively hold potentials of the plurality of data lines. N first holding capacitors are arranged in a column direction Y, each of the first holding capacitors having an electrode width that is smaller than a width of N pixel circuits arranged adjacent to each other in a row direction X, and that is equal to or larger than a width of one pixel circuit.

Disclosed is a method for manufacturing a capacitor of a semiconductor device. The method includes the steps of providing a substrate having a storage node plug, forming a PE-TEOS layer and a hard mask exposing a storage node contact area on the substrate, forming a storage node contact having a side profile of a positive and negative pattern through etching the PE-TEOS layer, removing the hard mask by etching-back the hard mask, performing an annealing process with respect to a resultant structure, forming a silicon layer on the silicon substrate, which passes through the annealing process, coating a photoresist film on an entire surface of the substrate, forming a storage node electrode by etching-back the photoresist film and the silicon layer, removing a remaining photoresist film, and forming a dielectric layer and a silicon layer on a storage node electrode structure.

The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material. Therefore, it is unnecessary to perform the batch forming of the control gate material, the interpoly dielectric film material, and the floating gate material in the case of processing the control gates, thereby ensuring adequate interpoly dielectric film capacitance.