Non-volatile memory devices and methods of operating the same

Abstract

Non-volatile memory devices and methods of operating the same are disclosed. A non-volatile memory device includes a semiconductor substrate. A tunnel insulating layer and a gate electrode are on the semiconductor substrate. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with a plurality of layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than a minimum field in the blocking insulation layer. A minimum field established at a blocking insulation layer can be stronger than a minimum field established at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than that of charges through the blocking insulation layer. Therefore, it may be possible to use lower operation voltages, obtain higher program and erase speeds, and/or obtain a greater difference between threshold values of a program threshold voltage and an erase threshold voltage. As a result, a multi-valued non-volatile memory device may be formed therefrom.

Description

RELATED APPLICATIONS [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10 / 795,537, filed Mar. 8, 2004, which is a continuation-in-part of U.S. patent application Ser. No. 10 / 184,328, filed Jun. 27, 2002, and which is related to and claims priority from Korean Patent Application No. 2003-26776, filed on Apr. 28, 2003, from Korean Patent Application No. 2002-05622, filed on Jan. 31, 2002, and from Korean Patent Application No. 2001-37421, filed on Jun. 28, 2001, and this application is related to and claims priority from Korean Patent Application No. P2005-30456, filed Apr. 12, 2005, and from Korean Patent Application No. P2005-42096, filed, May 19, 2005, the contents of each of which are herein incorporated by reference in their entirety.FIELD OF THE INVENTION [0002] The present invention relates to a non-volatile memory devices. BACKGROUND OF THE INVENTION [0003] Two types of non-volatile memory devices are floating gate type memory devices and fl...

AI Technical Summary

Problems solved by technology

A thicker tunneling insulating layer may result in an increased operating voltage for the memory device and an increased complexity of associated peripheral circuitry.

Consequently, it may be more difficult to provide high integration density and low power consumption for floating gate type memory devices than for floating trap type memory devices.

Differences between the energy band gaps may result in potential barriers at the interfaces between the materials.

The thickness of the silicon oxide layer may affect the data retention tim

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