Efuse devices and efuse arrays thereof and efuse blowing methods

Abstract

The invention provides an efuse array, an efuse device and an efuse blowing method. The efuse array comprises a plurality of word lines, at least one bit line, a plurality of cells, a plurality of first selection devices, and at least one second selection device. The word lines are interlaced with the bit line. The cells are disposed in an array, and each corresponds to one set of the interlaced word line and bit line. Each first selection device is coupled to one of the word lines, and the second selection device is coupled to the bit line. The invention is capable of reducing the sensing circuits needed for blowing the cells, and reducing the occupied area of the efuse array.

Description

technical field

[0001] The present invention relates to an efuse device, and more particularly to an efuse array with two-dimensional decoding. Background technique

[0002] Figure 1 shows a conventional electric fuse (efuse) array. Referring to FIG. 1 , a 4 x 2 electric fuse array 10 is taken as an example for illustration. The e-fuse array 10 includes a plurality of memory cells (ie, fuses 100-107) and blowing transistors T100-T107. Each of the fusing transistors T100-T107 is coupled between a memory cell and a reference voltage. When it is determined to burn the memory cell in the write mode, the corresponding fusing transistor is turned on, and the fusing current on the source line SL is supplied to the determined memory cell through the turned-on fusing transistor to fuse Burn this memory cell. For example, in the write mode, if it is decided to burn the memory cell 100, the fusing transistor T100 is turned on, and the fusing current on the source line SL is supplie...

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