Preparation method of silicon nano-wire field-effect transistor

Abstract

The invention relates to the field of microelectronic apparatus manufacture, and discloses a top-down preparation method of a vertical silicon nano-wire gate field-effect transistor. The vertical silicon nano-wire gate field-effect transistor includes a semiconductor substrate, a nano-wire channel region vertically arranged on the semiconductor substrate and an annular grid conductive layer arranged out of the channel. The nano-wire channel region is provided with an active conductive layer; the upper part is doped with n impurity to serve as a source end n area; the semiconductor substrate contacting with the bottom of the drain conductive layer is doped with n impurity to serve as a drain end n area; and a non-symmetrical Halo-doped structure p+ region is added between the source end and the channel. The method for preparing the vertical silicon nano-wire gate field-effect transistor can well control the consistency of the position and size of the nano-wire, thus simplifying the manufacture process and reducing the manufacture cost.

Description

Technical field: [0001] The invention relates to the field of manufacturing nanometer electronic devices, in particular to a method for preparing a field-effect transistor surrounded by vertical silicon nanowires. Background technique: [0002] The increase in integrated circuit density, the continuous improvement in performance, and the continuous decline in cost benefit from the continuous reduction in the size of MOS devices. However, when the size of MOS devices is reduced to the nanometer level, the short channel and subthreshold performance degrade rapidly. In order to suppress the performance degradation of MOS devices and enable integrated circuits to still have good performance at the nanometer level, innovations can be made in terms of device structure. Change the traditional planar device structure to a multi-gate MOS structure to increase the control ability of the gate to the channel. Because the entire channel is surrounded by the gate, the surrounding gate d...

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Problems solved by technology

The hollowing process is difficult to achieve uniform silicon pillars, and it is easy to cause small silicon pillars to break and collapse

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