Manufacturing method of three-dimensional array grid-last type Si-NWFET (Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator)

Abstract

The invention discloses a manufacturing method of a three-dimensional array grid-last type Si-NWFET (Silicon-Nanowire Field Effect Transistor) based on an SOI (Silicon On Insulator). The manufacturing method comprises the following steps of: alternatively growing silicon layers and germanium-silicon layers on the SOI, forming a fin-shaped active region, forming silicon nanowires in the fin-shaped active region, depositing amorphous carbon in a groove as a virtual isolating layer, then carrying out a grid-last process, and finally and simultaneously carrying out deposition on a groove isolating medium and an interlayer isolating medium. The manufacturing method disclosed by the invention has the advantages that due to existence of an oxygen embedding layer in the SOI, the isolating effect between a grid and an SOI substrate is effectively improved, and the adoption of the grid-last process is beneficial to the control of the profile of the grid and the electrical property of a device; the utilization of the amorphous carbon as the virtual isolating layer is beneficial to the control of the profiles of the grid and the grid groove; and in addition, the silicon-nanowire field effect transistor (Si-NWFET) structure is designed by adopting a three-dimensional array silicon-nanowire structure, so that the number of the nanowires is increased, and the current driving capability of the device is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to an SOI-based three-dimensional array gate-back Si-NWFET manufacturing method. Background technique [0002] It has always been the goal pursued by the development of microelectronics industry to increase the working speed and integration of chips and reduce the power consumption density of chips by reducing the size of transistors. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few layers of oxygen atoms thick. It is difficult to improve performance by reducing the size of traditional field effect transistors, mainly because of the short Channeling and gate leakage destroy the switching performance of transistors. [0003] Nanowire Field Effect Transistor (NWFET, Nano-Wire MOSFET) is expected t...

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Problems solved by technology

This method can realize the vertically stacked silicon nanowire field effect transistor structure, but there is a disadvantage: when the SiGe layer is oxidized, Ge will be concentrated on the surface of the Si layer. SiGe alloy

Because GeO2 is soluble in water, it makes the subsequent process face great inconvenience. In addition, the dielectric constant of GeO2 is smaller than that of SiO2, and the interface state between GeO2 and Si is larger, so it is not suitable as the gate oxide layer of field effect transistor (FET).

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