Double-layer isolation longitudinal stacked semiconductor nanowire MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Abstract

The invention provides a double-layer isolation longitudinal stacked semiconductor nanowire MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The double-layer isolation longitudinal stacked semiconductor nanowire MOSFET comprises a semiconductor substrate, a first semiconductor nanowire MOSFET, a second semiconductor nanowire MOSFET, an isolation medium layer and a buried oxide layer, wherein the first semiconductor nanowire MOSFET further comprises a first semiconductor nanowire group and a first gate oxide layer; the second semiconductor nanowire MOSFET further comprises a second semiconductor nanowire group and a second gate oxide layer; the isolation medium layer is arranged between the first semiconductor nanowire MOSFET and the second semiconductor nanowire MOSFET; and the buried oxide layer is arranged between the first semiconductor nanowire MOSFET and the semiconductor substrate. According to the invention, by using the structural design that the first semiconductor nanowire MOSFET has the longitudinal stacked first semiconductor nanowire group and the second semiconductor nanowire MOSFET has the longitudinal stacked second semiconductor nanowire group, the process can be debugged in a completely independent way and high integration level of the device is obtained. At the same time, by using the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention, the electrical property of the field effect transistor is improved and the device current driving capability is improved in multiples; and the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention is suitable for the technical field of advanced nanodevices.

Description

technical field [0001] The invention relates to the technical field of semiconductor field effect transistors, in particular to a double-layer isolation vertically stacked semiconductor nanowire MOSFET. Background technique [0002] It has always been the goal pursued by the development of microelectronics industry to increase the working speed and integration of chips and reduce the power consumption density of chips by reducing the size of transistors. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few layers thick of oxygen atoms. It is difficult to improve the performance by reducing the size of traditional field effect transistors, mainly because of the short channel Channel effect and gate leakage current deteriorate the switching performance of the transistor. [0003] Nanowire Field Effect Transi...

AI Technical Summary

Problems solved by technology

[0014] The present invention is aimed at the prior art, the existing semiconductor nanowire MOSFET can not realize the separation structure of NMOS and PMOS, can not adjust the gate work function and gate resistivity for NMOS and PMOS respectively, and realize the separate structure for NMOS and PMOS The process of source-drain ion implantation is difficult, and the current driving capability of the device is limited by the cross-sectional area of ​​the semiconductor nanowire, which cannot further increase the current driving capability of the device. Provide a double-layer isolated vertically stacked semiconductor nanowire MOSFET

Images