Bulk-silicon-based manufacturing method for vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET)

Abstract

The invention discloses a bulk-silicon-based manufacturing method for a vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET). The method comprises the following steps of: providing a bulk silicon substrate on which SiGe layers and Si layers are alternately grown; photo-etching and etching the SiGe layers and the Si layers to form fin-shaped active regions, and taking the residual SiGe layers and the residual Si layers as source and drain regions; selectively etching and removing the SiGe layers in the fin-shaped active regions to form silicon nano-wires which are vertically stacked; forming a virtual isolation layer on the bulk silicon substrate between the source region and the drain region; forming a gate trench in the virtual isolation layer; forming gate oxide layers on the silicon nano-wires; forming a gate in the gate trench; removing the virtual isolation layer to form an isolated trench; and forming an isolation dielectric layer in the isolated trench. Due to the adoption of the virtual isolation layer, control over the contour of the gate trench is facilitated; the conventional gate oxide layers are adopted; and the silicon nano-wires are vertically stacked, so that the integration level and current driving capability of a device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a bulk silicon-based vertically stacked gate-back type silicon nanowire field effect transistor (SiNWFET) preparation method. Background technique [0002] In the prior art, reducing the size of transistors to increase the working speed and integration of chips and reduce the power consumption density of chips has always been the goal pursued by the development of the microelectronics industry. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few layers thick of oxygen atoms. It is difficult to improve the performance by reducing the size of traditional field effect transistors, mainly because of the short channel Channel effect and gate leakage current deteriorate the switching performance of the tran...

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Problems solved by technology

This method can realize the vertically stacked silicon nanowire field effect transistor structure, but there is a disadvantage: when the SiGe layer is oxidized, Ge will be concentrated on the surface of the Si layer. SiGe alloy

Because GeO2 is soluble in water, it makes the subsequent process face great inconvenience. In addition, the dielectric constant of GeO2 is smaller than that of SiO2, and the interface state between GeO2 and Si is larger, so it is not suitable as the gate oxide layer of field effect transistor (FET).

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