Video transmission design method and system based on FPGA

Abstract

The invention belongs to the technical field of high-definition video acquisition and transmission, and discloses a video transmission design method and system based on an FPGA (Field Programmable Gate Array). According to the method, through the design of a UDP / IP / MAC receiving module, a UDP / IP / MAC sending module, a PHY chip working mode configuration module, a DDR3SDRAM controller and an HDMI control module, under the condition that an IP core is not called, a hardware description language Verilog HDL is used for achieving Ethernet video transmission controller digital circuit bottom layer driving; without an external physical layer chip, a Verilog HDL drive circuit is established through a Verilog HDL to complete an HDMI physical layer sending function, and finally data interaction with an upper computer is completed. According to the invention, high-speed transmission and display of video data are finally realized; according to the invention, the area and the cost of a hardware board card are saved, and the universality, the flexibility and the compatibility of the system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-definition video acquisition and transmission, and in particular relates to a video transmission design method and system based on FPGA. Background Art

[0002] At present, with the continuous improvement of microelectronics, optoelectronic communications, digital video, multimedia technology and modern sensor technology, the widespread application and rapid development of integrated circuits, especially the widespread popularization of FPGA (programmable gate array), analog video systems are developing towards digital video systems and gradually replacing them. At the same time, digital video systems are also developing towards high integration, flexibility, versatility, scalability, compatibility, high resolution, intelligence and ultra-long-distance transmission, which has prompted video systems to continuously update their acquisition, caching, processing, transmission and display technologies. FPGA-based video systems have gradually become popular.

[0003] Ethernet transmission technology has been widely used in some military enterprises and some civilian enterprises due to its advantages such as long transmission distance, high resistance, and low loss in ultra-long distance transmission. The development of high-speed video transmission technology has led to the widespread popularization of Gigabit Ethernet technology.

[0004] Through the above analysis, the problems and defects of the prior art are as follows: in the transmission of video data in the prior art, the area and cost of the hardware board are high, and the versatility, flexibility and compatibility of the system are poor. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the disclosed embodiment of the present invention provides a video transmission design method and system based on FPGA.

[0006] The technical scheme is as follows: a design method for video transmission based on FPGA, which implements the underlying driver of the digital circuit of the Ethernet video transmission controller using the hardware description language Verilog HDL without calling the IP core through the design of a UDP / IP / MAC receiving module, a UDP / IP / MAC sending module, a PHY chip working mode configuration module, a DDR3 SDRAM controller and an HDMI control module; in the absence of an external physical layer chip, a Verilog HDL driving circuit is built through Verilog HDL to complete the HDMI physical layer sending function, and finally completes the data interaction with the host computer.

[0007] Furthermore, the design of the UDP / IP / MAC receiving module includes: the design of a receiving-end data sampling conversion module, a cross-clock domain clock synchronization module, and a pixel point information extraction module;

[0008] The receiving end data sampling conversion module design includes: using the primitive IDDR inside the FPGA to convert the double-edge 4-bit data into single-edge 8-bit data;

[0009] The design of the cross-clock domain clock synchronization module includes: performing cross-clock domain processing on the phase mismatch or clock frequency inconsistency between the accompanying clock PHY_clk transmitted from the PHY chip end received by the receiving end data sampling conversion module and the system clock in the FPGA, and crossing the data from the physical layer clock domain to the FPGA system clock domain;

[0010] The design of the pixel point information extraction module includes: extracting RGB image information from data and enable signals transmitted through the cross-clock domain processing module.

[0011] Furthermore, in the design of the pixel information extraction module, a multiplier circuit is added. According to the instantiated code template written by the multiplier circuit, the result of multiplying the image length and width information w and h is used as the cache address threshold of the DDR3 SDRAM controller.

[0012] Further, the UDP / IP / MAC sending module design includes the design of the network layer IP protocol, the transport layer UDP protocol, and the data packet sending module, the checksum calculation module, the CRC check algorithm module and the sending end data sampling conversion module of the data link layer MAC sublayer;

[0013] The design of the data packaging and sending module includes: filling the preamble, MAC address, IP header and UDP header information before sending the data, filling it into a protocol data packet that can be recognized by the PC;

[0014] The design of the verification and calculation module includes: adding a verification or error correction algorithm to the encoding of the data;

[0015] The design of the data sampling conversion module at the transmitting end includes: converting the single-edge 8-bit data into double-edge 4-bit data, and connecting with the RGMII interface of the external physical layer PHY chip.

[0016] Further, the PHY chip working mode configuration module design includes:

[0017] The CMODE0, CMODE1, CMODE2 and CMODE3 configuration pins are connected to resistors of different values, and the address of the PHY chip is determined by the external resistance value of CMODE2 and the external resistance value of CMODE3, and the PHY chip is awakened to work normally; the PHY chip is also configured with two pins, MDC and MDIO, where MDC is a clock line and MDIO is a bidirectional data line;

[0018] After the PHY chip performs hardware configuration or register configuration, it works normally according to the configuration, and the physical layer chip provides multiple interface standards to the data link layer MAC sublayer, including MII media independent interface, Reduced MII interface, GMII Gigabit media independent interface and Reduced GMII interface.

[0019] Furthermore, the MDC and MDIO configure specific function registers in the PHY chip according to the read and write timing sequence, configure the PHY chip to a restart_auto_negatiation (auto-negatiation) working mode, and write the value of the specific function register according to the read and write timing sequence.

[0020] Furthermore, the HDMI control module design includes the design of a VGA control module, an 8b10b encoding module and a parallel-to-serial module. After the design is completed, data interaction between the HDMI transmitter and the host computer is realized.

[0021] Further, the design of the VGA control module includes: using the VGA interface timing of 640*480@60Hz, calculating the pixel clock clk=800*525*60=25.2MHz, supporting hot plugging and audio transmission;

[0022] The 8-bit to 10-bit module design includes: the number of 1s and 0s in the encoded binary data is kept consistent to make the DC balanced;

[0023] The parallel-to-serial module design includes: when processing parallel-to-serial conversion, using the primitive OSERDESE2 provided by Xilinx, OSERDESE2 supports converting parallel data into 2, 8, 10 and 14-bit serial serialized data, configuring OSERDESE2 to convert parallel data into 10-bit mode, cascading two OSERDESE2 primitives to obtain 10-bit video data, one of which serves as the host and the other as the slave.

[0024] Another object of the present invention is to provide a design system for video transmission based on FPGA, which implements the design method for video transmission based on FPGA, and the system comprises:

[0025] The UDP / IP / MAC receiving module, UDP / IP / MAC sending module, PHY chip working mode configuration module, DDR3SDRAM controller and HDMI control module realize data self-loop transmission and reception. Without calling the IP core, the hardware description language Verilog HDL is used to implement the underlying driver of the digital circuit of the Ethernet video transmission controller. In the absence of an external physical layer chip, the Verilog HDL driver circuit is built through Verilog HDL to complete the HDMI physical layer sending function, and finally complete the data interaction with the host computer.

[0026] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows: the present invention provides a design and implementation process of a Gigabit Ethernet data transmission controller and an HDMI transmitter controller based on FPGA, and uses Verilog HDL to complete the digital logic circuit design of the data link layer MAC sublayer, the transport layer UDP protocol, and the network layer IP protocol without calling the IP core. In the absence of an external HDMI physical layer chip, the drive circuit is directly built inside the FPGA using Verilog HDL to complete the physical layer transmission function, and finally realizes high-speed transmission and display of video data. The present invention saves the area and cost of hardware boards and improves the versatility, flexibility, and compatibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0028] Figure 1 It is a schematic diagram of a video transmission design system based on FPGA provided by an embodiment of the present invention;

[0029] Figure 2 It is a schematic diagram of a video transmission design system based on FPGA provided by an embodiment of the present invention;

[0030] Figure 3 Configure the schematic diagram for the PHY chip board;

[0031] Figure 4 This is the read and write timing waveform of MDC;

[0032] Figure 5 This is the MDIO read and write timing waveform;

[0033] In the figure: 1. UDP / IP / MAC receiving module; 2. UDP / IP / MAC sending module; 3. PHY chip working mode configuration module; 4. DDR3 SDRAM controller; 5. HDMI control module. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0035] Embodiment 1, the design method of video transmission based on FPGA provided by the embodiment of the present invention implements Gigabit Ethernet video transmission controller and HDMI transmitter controller based on FPGA design, including the configuration principle and configuration mode of the physical layer PHY chip, the transport layer UDP protocol, the network layer IP protocol and the data link layer MAC sublayer implementation scheme, and implements the Ethernet video transmission controller digital circuit bottom layer driver using the hardware description language Verilog HDL without calling the IP core. In the absence of an external physical layer chip, the Verilog HDL driver circuit is built by Verilog HDL to implement the HDMI physical layer transmission function, and finally complete the data interaction with the host computer. The present invention saves the area and cost of the hardware board, and improves the versatility, flexibility and compatibility of the system.

[0036] like Figure 1 As shown, the design system of video transmission based on FPGA provided by the embodiment of the present invention includes:

[0037] The UDP / IP / MAC receiving module 1, the UDP / IP / MAC sending module 2, the PHY chip working mode configuration module 3, the DDR3SDRAM controller 4 and the HDMI control module 5 realize data self-loop transmission and reception, that is, the Ethernet transmission function is completed and the test system is also built. Figure 2 This is the principle of the design system of video transmission based on FPGA provided by the embodiment of the present invention.

[0038] Exemplarily, the configuration principle and configuration method of the physical layer PHY chip are driven;

[0039] First, the PHY chip working mode configuration module 3 is designed, that is, the PHY hardware configuration and register configuration module design. The physical layer is located at the lowest layer of the entire hybrid model. It can be divided into three layers in more detail, namely the physical medium related sublayer, the physical medium additional sublayer and the physical coding sublayer. At present, many dedicated chips have the functions realized by these three layers. Such chips can be directly connected to the RJ45 network card interface. If such physical layer chips are to work properly, special configuration is required.

[0040] like Figure 3The following is the schematic diagram of the PHY chip board configuration. Figure 3 You can see that the CMODE0, CMODE1, CMODE2, and CMODE3 configuration pins are connected to resistors of different values. The values ​​of these resistors are fixed. When the external resistor value of CMODE2 is 22.6K and the external resistor value of CMODE3 is 4.02K, the address of the PHY chip can be determined as 5'b00000, and the chip is awakened and works normally. If the board needs to involve multiple PHY chips and multiple network interfaces, you only need to change the external resistor value to determine the chip address. These resistor values ​​can be determined according to the PHY chip manual. In addition to the hardware configuration method, PHY also supports interface register configuration. Figure 3 It can be seen that the PHY chip has two pins, MDC and MDIO, where MDC is the clock line and MDIO is the bidirectional data line.

[0041] like Figure 4 and Figure 5 They are the read and write timing waveforms of MDC and MDIO, which is a half-duplex IIC-like bus. The specific function registers in the PHY chip can be configured according to the read and write timing. This system needs to configure the PHY chip to restart_auto_negatiation (auto-negatiation) working mode. The following are the values ​​that need to be written into the specific function registers according to the read and write timing:

[0042] always@(index)

[0043] begin

[0044] case(index)

[0045] 0:power_down<=24'h001900;

[0046] 1:restart_auto_negatiation<=24'h001100;

[0047] default:reg_data<=24'h001300;

[0048] endcase

[0049] end.

[0050] For example, after the PHY chip is configured with hardware or registers, it can work normally according to the configuration requirements. The physical layer chip provides multiple interface standards to the data link layer MAC sublayer, such as MII (media independent interface), RMII (Reduced MII), GMII (Gigabit Media Independent Interface) and RGMII (Reduced GMII). The difference between GMII and RGMII interface is that GMII uses 8 data lines and 8 pins for control, while RGMII uses 4 data lines and 4 pins for control. The advantage of the Reduced version is that it can save half of the data lines. In the case of tight FPGA pin resources, Reduced can play its advantages. Although the data lines are reduced by half, the corresponding reference clock frequency needs to be doubled or double-edge sampling is used. For example, the working clock of PHY is 125MHz. Under the same circumstances, if the data lines are reduced by half, the bandwidth is 125MHz / s*4=500Mb / s. If it is still single-edge sampling at this time, the transmission bandwidth of 1.0Gb / s cannot be achieved. To generate 1.0G bandwidth with a 125MHz clock on the original basis, a dual-edge sampling mode is required, that is, 4 bits on the rising edge and 4 bits on the falling edge. At this time, the bandwidth is 125MHz / s*4*2=1000Mb / s.

[0051] Exemplarily, the design of UDP / IP / MAC receiving module 1, i.e., the design of Gigabit Ethernet receiving end controller;

[0052] After the PHY chip configuration is completed, the Ethernet physical layer works normally. The Gigabit Ethernet receiver controller is further designed, which mainly includes the receiver data sampling and conversion module, the cross-clock domain clock synchronization module and the pixel information extraction module.

[0053] The receiving end data sampling and conversion module (IDDR data sampling and conversion module) is designed. Usually, FPGA uses single-edge sampling to process data. Since the design uses the RGMII interface, the PHY chip outputs dual-edge sampling data to the FPGA MAC sublayer. Therefore, it is necessary to use the primitive IDDR inside the FPGA to convert the dual-edge 4-bit data into single-edge 8-bit data and perform the conversion inside the FPGA. Otherwise, the meaning of data transmission is lost and the function of the original data is lost.

[0054] After designing the cross-clock domain clock synchronization module and completing the IDDR data sampling and conversion module, the dual-edge 4-bit data transmitted by PHY is converted into single-edge 8-bit data, as well as the corresponding data synchronization enable signal. However, the problem is that the accompanying clock PHY_clk transmitted from the PHY chip is inconsistent with the system clock in the FPGA, and there will be a phase mismatch or inconsistent clock frequency, which will lead to metastable problems during data transmission and cause errors in the received data. Therefore, cross-clock domain processing is required to cross the data from the physical layer clock domain to the FPGA system clock domain.

[0055] When designing the pixel information extraction module, the data and enable signal pass through the cross-clock domain processing module. The transmitted data includes not only the RGB data information from the host computer, but also the destination MAC address, source MAC address and preamble information. These data need to be filtered out. Therefore, after the data passes through the cross-clock domain processing module, a pixel information extraction module, i.e., an RGB image information extraction module, should also be designed. This is a crucial step. In addition, a multiplier circuit needs to be added to this pixel information extraction module. The following is an instantiation code template written by the multiplier circuit. The result of multiplying the image length and width information w and h is used as the cache address threshold of the DDR3 SDRAM controller 4.

[0056] Exemplarily, the design of UDP / IP / MAC sending module 2, i.e., the design of the sending end controller;

[0057] After completing the Gigabit Ethernet receiver controller, it is also necessary to design and implement the Gigabit Ethernet transmitter controller, which mainly includes the network layer IP protocol, the transport layer UDP protocol, and the data packet transmission module, checksum calculation module, CRC check algorithm module and the transmitter data sampling conversion module of the data link layer MAC sublayer.

[0058] The difference between the transmitter controller and the receiver controller is that the receiver only needs to receive the data from the host computer in time sequence and extract the image data information. In this process, the preamble and MAC address information sent by the host computer need to be filtered out. When the FPGA board sends data to the PC, if it is just data transmission, the PC cannot recognize it.

[0059] Among them, the design and implementation of the data packaging and sending module are carried out. The difference between the sending end controller and the receiving end controller is that the receiving end only needs to receive the data from the host computer in time sequence and extract the image data information. In this process, the preamble and MAC address information sent by the host computer need to be filtered out. When the FPGA board sends data to the PC, if it is just data transmission, the PC cannot recognize it. Therefore, it is necessary to fill in the preamble, MAC address, IP header, UDP header and other information before sending the data, and fill it into a protocol data packet that the PC can recognize.

[0060] Design and implement the checksum calculation module. In the field of communication, data may be erroneous during transmission due to some interference. In order to reduce the occurrence of such errors, some check or error correction algorithm support will be added to the data encoding while improving the hardware reliability. The most common way is to add a check mechanism or check bit to the data. This kind of coding with error correction capability is called a check code.

[0061] The sending end data sampling conversion module (ODDR data sampling conversion module) is designed and implemented. When the host computer sends data to the FPGA through the sending end of Ethernet, it needs to pass through the physical layer PHY chip. The configuration interface of the PHY chip in this design is the RGMII interface. When the clock frequency and transmission rate remain unchanged, the dual-edge sampling method should be used for transmission. However, the FPGA always works in a single-edge sampling mode. At this time, the role of the IDDR module is to convert the dual-edge 4-bit data into single-edge 8-bit data. After the data is processed by the FPGA, the single-edge 8-bit data needs to be converted into dual-edge 4-bit data through the ODDR module, and connected to the external physical layer PHY chip RGMII interface.

[0062] Exemplarily, the HDMI control module 5 is designed, i.e., the HDMI transmission controller is designed;

[0063] The modular functions of the Gigabit Ethernet transmission controller have been implemented previously. This includes the PHY working principle and configuration method of the receiving end, the cross-clock domain processing module, and the RGB image information extraction module; the data framing module, checksum module, CRC check module, and ODDR module of the transmitting end. The modular functions of the HDMI transmitter controller are further implemented, and the Verilog HDL driver circuit is built with Verilog HDL to replace the physical layer chip transmitter function.

[0064] The required HDMI control module 5 design includes a VGA control module, an 8b10b encoding module, and a parallel-to-serial module. After the design is completed, data interaction between the HDMI transmitter and the host computer can be realized.

[0065] The VGA control module is designed and implemented. VGA is a universal image and video transmission protocol with advantages such as high resolution and rich colors. It is widely used in fields such as color displays. However, its shortcomings of not supporting hot plugging and audio transmission also limit its application field. The present invention uses a 640*480@60Hz VGA interface timing, and calculates the pixel clock clk=800*525*60=25.2MHz. It should be noted that both the line synchronization signal and the field synchronization signal are valid at low level, and the line synchronization signal must also be provided in the invalid area of ​​the data line.

[0066] Design an 8-bit to 10-bit module. After the external video image data is converted into information of corresponding resolution pixels by the VGA control module, an 8-bit to 10-bit conversion module needs to be designed. The purpose is to maintain DC balance and keep the number of 1 and 0 in the encoded binary data consistent. The biggest problem that DC balance overcomes is that when there are multiple bits of logic 1 and logic 0 in the high-speed serial stream that have not changed, the signal conversion will cause signal transmission errors due to the voltage level relationship.

[0067] After designing the parallel-to-serial module and completing the implementation of the 8-bit to 10-bit encoding module, the last module, the serial-to-parallel conversion module, needs to be designed. When processing the parallel-to-serial conversion, the primitive OSERDESE2 provided by Xilinx is also used. OSERDESE2 supports converting parallel data into 2, 8, 10, and 14-bit serial serialized data. Here, OSERDESE2 is configured to convert parallel data into 10-bit mode. In order to obtain 10-bit video data, two OSERDESE2 primitives need to be cascaded, one as the host and the other as the slave.

[0068] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A design method for video transmission based on FPGA, characterized in that: The method uses the hardware description language Verilog HDL to realize the bottom-level driver of the digital circuit of the Ethernet video transmission controller without calling the IP core through the design of a UDP / IP / MAC receiving module (1), a UDP / IP / MAC sending module (2), a PHY chip working mode configuration module (3), a DDR3 SDRAM controller (4) and an HDMI control module (5); in the absence of an external physical layer chip, a Verilog HDL driving circuit is built by Verilog HDL to complete the HDMI physical layer sending function, and finally completes the data interaction with the host computer.

2. The design method of video transmission based on FPGA according to claim 1, characterized in that: The design of the UDP / IP / MAC receiving module (1) includes the design of a receiving end data sampling conversion module, a cross-clock domain clock synchronization module and a pixel point information extraction module; The receiving end data sampling conversion module design includes: using the primitive IDDR inside the FPGA to convert the double-edge 4-bit data into single-edge 8-bit data; The design of the cross-clock domain clock synchronization module includes: performing cross-clock domain processing on the phase mismatch or clock frequency inconsistency between the accompanying clock PHY_clk transmitted from the PHY chip end received by the receiving end data sampling conversion module and the system clock in the FPGA, and crossing the data from the physical layer clock domain to the FPGA system clock domain; The design of the pixel point information extraction module includes: extracting RGB image information from data and enable signals transmitted through the cross-clock domain processing module.

3. The design method of video transmission based on FPGA according to claim 2, characterized in that: In the design of the pixel point information extraction module, a multiplier circuit is also added. According to the instantiated code template written by the multiplier circuit, the result obtained by multiplying the image length and width information w and h is used as the cache address threshold of the DDR3 SDRAM controller (4).

4. The design method of video transmission based on FPGA according to claim 1, characterized in that: The design of the UDP / IP / MAC sending module (2) includes the design of the network layer IP protocol, the transport layer UDP protocol, and the data packet sending module, the checksum calculation module, the CRC check algorithm module and the sending end data sampling conversion module of the data link layer MAC sublayer; The design of the data packaging and sending module includes: filling the preamble, MAC address, IP header and UDP header information before sending the data, filling it into a protocol data packet that can be recognized by the PC; The design of the verification and calculation module includes: adding a verification or error correction algorithm to the encoding of the data; The design of the data sampling conversion module at the transmitting end includes: converting the single-edge 8-bit data into double-edge 4-bit data, and connecting with the RGMII interface of the external physical layer PHY chip.

5. The design method of video transmission based on FPGA according to claim 1, characterized in that: The PHY chip working mode configuration module (3) is designed to include: The CMODE0, CMODE1, CMODE2 and CMODE3 configuration pins are connected to resistors of different values, and the address of the PHY chip is determined by the external resistance value of CMODE2 and the external resistance value of CMODE3, and the PHY chip is awakened to work normally; the PHY chip is also configured with two pins, MDC and MDIO, where MDC is a clock line and MDIO is a bidirectional data line; After the PHY chip performs hardware configuration or register configuration, it works normally according to the configuration, and the physical layer chip provides multiple interface standards to the data link layer MAC sublayer, including MII media independent interface, Reduced MII interface, GMII Gigabit media independent interface and Reduced GMII interface.

6. The design method of video transmission based on FPGA according to claim 5, characterized in that: The MDC and MDIO configure the specific function registers in the PHY chip according to the read and write timing, configure the PHY chip to the restart_auto_negatiation (auto-negatiation) working mode, and write the values ​​of the specific function registers according to the read and write timing.

7. The design method of video transmission based on FPGA according to claim 1, characterized in that: The design of the HDMI control module (5) includes the design of a VGA control module, an 8b10b encoding module and a parallel-to-serial module. After the design is completed, data interaction between the HDMI transmitter and the host computer is realized.

8. The design method of video transmission based on FPGA according to claim 7, characterized in that: The design of the VGA control module includes: using the VGA interface timing of 640*480@60Hz, calculating the pixel clock clk=800*525*60=25.2MHz, supporting hot plugging and audio transmission; The 8-bit to 10-bit module design includes: the number of 1s and 0s in the encoded binary data is kept consistent to make the DC balanced; The parallel-to-serial module design includes: when processing parallel-to-serial conversion, using the primitive OSERDESE2 provided by Xilinx, OSERDESE2 supports converting parallel data into 2, 8, 10 and 14-bit serial serialized data, configuring OSERDESE2 to convert parallel data into 10-bit mode, cascading two OSERDESE2 primitives to obtain 10-bit video data, one of which serves as the host and the other as the slave.

9. A design system for video transmission based on FPGA, characterized in that: The system implements the FPGA-based video transmission design method as described in any one of claims 1 to 8, and the system includes: The UDP / IP / MAC receiving module (1), the UDP / IP / MAC sending module (2), the PHY chip working mode configuration module (3), the DDR3 SDRAM controller (4) and the HDMI control module (5) realize data self-loop transmission and reception. Without calling the IP core, the hardware description language Verilog HDL is used to realize the underlying driver of the digital circuit of the Ethernet video transmission controller; without an external physical layer chip, the Verilog HDL driver circuit is built by Verilog HDL to complete the HDMI physical layer transmission function, and finally complete the data interaction with the host computer.

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