Data packet low-delay caching device and method for exchange equipment

Abstract

The invention discloses a data packet low-delay caching device and method for switch equipment. The device comprises a data packet aggregation module, a scheduler module, a data receiving module, a caching region module, a dynamic memory distribution module, a data sending module, a memory block state table module, and an idle memory block first-in first-out queue module. The method comprises thefollowing steps: the aggregation module aggregates a data packet as an aggregated data block with fixed size; the scheduler module distributes a caching address for the aggregated data block; the dynamic memory management module maintains memory block use information; the data receiving module moves the aggregated data block to the corresponding DRAM caching unit; an output port sends a read application to the scheduler module, and the data sending module outputs the data packet to the external from the caching region after the conflict detection. The delay of the cache is lowered, and the processing speed of the exchange equipment is improved.

Description

technical field [0001] The invention belongs to the technical field of communication, and further relates to a data packet low-latency buffering device and method for switching equipment in the technical field of communication network. The invention can be used in switching equipment to realize fast and low-delay buffering of data packets, and effectively improve the performance of the switching equipment. Background technique [0002] With the development of communication technology, people have higher and higher requirements for data transmission rate. The substantial increase in transmission rate has brought greater challenges to the read / write rate and capacity of buffers in Ethernet switches or router line cards. On the one hand, as the link rate and switching network rate increase, the rate at which packets enter and leave the buffer on the line card is required to be faster and faster. Usually, the data bus for memory reading and writing is shared. After a packet ar...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that after the communication device obtains the data packet, it first judges the cache mode according to the data packet information, and then transmits the data, which reduces the processing speed and increases the implementation complexity. In the high-speed switch, this method will produce Congestion or even packet loss

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