SSD controller based on read-write cache separation of STT-MRAM

A controller and cache technology, applied in the direction of static memory, memory system, digital memory information, etc., can solve the problems of insufficient data protection, increase system reliability, etc., and achieve the effect of simplifying system design complexity and increasing system reliability

Inactive Publication Date: 2016-05-04
CETHIK GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In order to overcome the above disadvantages, the present invention aims to provide an SSD controller based on STT-MRAM with separate read and write caches, and utilizes the high-speed read and write performance of

Method used

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  • SSD controller based on read-write cache separation of STT-MRAM
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  • SSD controller based on read-write cache separation of STT-MRAM

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Embodiment 1

[0018] Embodiment 1: as image 3 As shown, the SSD controller 3 is responsible for controlling data transmission between the FLASH storage array 4 and the host processor 2 . The read-write cache module 8 is responsible for caching all the data that needs to be written into the FLASH storage array 4, all the data that needs to be read from the FLASH storage array 4, the logical address (LBA) mapping table, the LBA modification increment table, the storage controller program and User configuration and other information, wherein the STT-MRAM memory 14 is responsible for caching all data that needs to be written into the FLASH storage array 4 and the LBA modification increment table; the DRAM memory 11 is responsible for caching all data that needs to be read from the FLASH storage array 4, LBA mapping table, controller program and user configuration. The communication interface between the read-write cache module 8 and the control logic module 7 is a DRAM interface, which can be...

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Abstract

The invention belongs to the technical field of computer memory equipment and particularly relates to an SSD controller based on read-write cache separation of an STT-MRAM. The SSD controller comprises a control logic module, a read-write cache module, an error correction module and a read-write driver module, wherein the read-write cache module comprises an STT-MRAM and a DRAM; the STT-MRAM caches all data required to be written in a FLASH memory array and an LBA modification increment table; and the DRAM caches all data required to be read from the FLASH memory array, an LBA mapping table, a controller program and user configuration. The SSD controller has the beneficial effects that the STT-MRAM is adopted as a write cache in the SSD controller; by utilizing high-speed read-write performance and power failure nonvolatile performance of the STT-MRAM, the problem of data protection shortage after power failure in the SSD controller is solved; and original power failure protection capacitor and power failure detection circuit in the controller are removed, so that the system reliability is improved and the complexity of system design is lowered.

Description

technical field [0001] The invention belongs to the technical field of computer storage devices, and in particular relates to an SSD controller based on STT-MRAM with read-write cache separation. Background technique [0002] There are currently two main types of computer external storage, magnetic disk (HDD) and solid-state drive (SSD). The main storage medium in SSD is flash memory (FLASHMEMORY). Compared with HDD, SSD has faster read and write speed, better random access performance, and lower power consumption for reading and writing. Therefore, with the improvement of FLASHMEMORY manufacturing process and the reduction of cost, SSD has been more and more widely used. [0003] The storage medium FLASH in the current commercial SSD mainly has two structures: NOR and NAND. Compared with NORFLASH, NANDFLASH has higher storage density and lower cost, and is currently the mainstream storage medium of SSD. However, whether it is NANDFLASH or NORFLASH, the read and write spe...

Claims

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Application Information

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IPC IPC(8): G06F12/0893G11C11/16
CPCG11C11/16G11C11/1673G11C11/1675G06F12/0893
Inventor 徐庶蒋信李辉辉左正笏韩谷昌刘瑞盛孟皓刘波
Owner CETHIK GRP
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