Error correction encoding method for dynamic random access memory (DRAM) buffer

A technology of error correction coding and error correction method, which is applied in the field of embedded hardware design and storage energy-saving design, can solve the problems of low efficiency and power consumption of intelligent refresh method, achieve wide commercial use, save power energy, and refresh cycle long effect

Inactive Publication Date: 2011-02-23
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But the smart refresh method is inefficient in the idle state, because no cache line will be

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  • Error correction encoding method for dynamic random access memory (DRAM) buffer
  • Error correction encoding method for dynamic random access memory (DRAM) buffer

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Embodiment Construction

[0029] The error correction encoding method for DRAM cache provided by the present invention will be described in further detail below in conjunction with the accompanying drawings:

[0030] figure 1 It is a flowchart of an embodiment of the present invention, and the method includes the following steps:

[0031] (1) Increase the refresh cycle and reduce the refresh frequency:

[0032] The distribution of DRAM in embedded hardware is relatively dense, and the possibility of bit data error depends heavily on the equipment material. In the power consumption of the entire system, the energy consumption required for DRAM and cache refresh accounts for a large part. Higher refresh frequency will greatly increase power consumption. In order to reduce energy consumption, the processor design considers the setting of the cache refresh cycle, too frequent will increase power consumption, and too long a cycle will easily cause data errors. Usually, it is necessary to select an optima...

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Abstract

The invention discloses an error corrosion encoding method for a dynamic random access memory (DRAM) buffer, which comprises the following steps of: (1) prolonging a refresh cycle of the DRAM buffer and reducing refresh frequency; and (2) encoding and decoding data in the buffer. In the method, refresh time is set according to the most error-prone bits, some error data is compensated by error correction technology which is powerful enough to correct a plurality of bits, which means the refresh time can be prolonged, thereby reducing power consumption.

Description

technical field [0001] The invention relates to the fields of embedded hardware design and storage energy-saving design, and in particular relates to an error correction coding method for DRAM cache. Background technique [0002] At present, advanced technology makes it possible to integrate a large embedded DRAM cache on the chip, which is denser than traditional SRAM, but the circuit must be refreshed in time to ensure data integrity, and DRAM is easily affected by equipment materials, which plays a decisive role in the refresh cycle , The power consumption point required for refresh accounts for the vast majority of the energy consumption of the entire system, so large DRAM integration brings the problem of increased refresh power consumption. [0003] The embedded DRAM cache is highly integrated and needs to be refreshed frequently. Otherwise, the information on some storage units will be lost due to power loss, making the data unavailable, and high-frequency refresh wil...

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Application Information

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IPC IPC(8): G11C29/42
Inventor 陈天洲虞保忠乔福明马建良乐金明
Owner ZHEJIANG UNIV
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