62 results about "Cmos mems" patented technology

A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space.

An acoustic transducer comprising a substrate; and a diaphragm formed by depositing a micromachined membrane onto the substrate. The diaphragm is formed as a single silicon chip using a CMOS MEMS (microelectromechanical systems) semiconductor fabrication process. The curling of the diaphragm during fabrication is reduced by depositing the micromachined membrane for the diaphragm in a serpentine-spring configuration with alternating longer and shorter arms. As a microspeaker, the acoustic transducer of the present invention converts a digital audio input signal directly into a sound wave, resulting in a very high quality sound reproduction at a lower cost of production in comparison to conventional acoustic transducers. The micromachined diaphragm may also be used in microphone applications.

A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.

An integrated MEMS System. CMOS and MEMS devices can be provided in order to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured. The integrated MEMS devices can include, but not exclusively, an combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices. The present technique provides an easy to use process that relies upon conventional process technology without substantial modifications to conventional equipment and process and reduces off-chip connections, which make the mass production of smaller and thinner units possible.

A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures.

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems / nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro / nano fabrication etching step to release the mechanical layer on the prefabricated mems / nems chips; positioning protective cap to package the integrated device over the mems / nems device area on the pre-fabricated chips.

A method for fabricating an integrated MEMS device and the resulting structure therefore. A control process monitor comprising a MEMS membrane cover can be provided within an integrated CMOS-MEMS package to monitor package leaking or outgassing. The MEMS membrane cover can separate an upper cavity region subject to leaking from a lower cavity subject to outgassing. Differential changes in pressure between these cavities can be detecting by monitoring the deflection of the membrane cover via a plurality of displacement sensors. An integrated MEMS device can be fabricated with a first and second MEMS device configured with a first and second MEMS cavity, respectively. The separate cavities can be formed via etching a capping structure to configure each cavity with a separate cavity volume. By utilizing an outgassing characteristic of a CMOS layer within the integrated MEMS device, the first and second MEMS cavities can be configured with different cavity pressures.