2-dimensional (2-d) convolver

Abstract

2-dimensional (2-D) convolution calculation is widely applied in the field of image processing. The invention discloses a 2-D convolver. By decomposing the 2-D convolution calculation into parallel calculation of multiple 1-D convolution calculation windows and adopting the strategy that image data are input in a row or column leading Zigzag scanning format, the capacity of an on-chip memory is reduced, and on-chip resource overhead is reduced; because the 2-D convolver can accept two different image data input formats of row or column leading Zigzag scanning formats, the 2-D convolver is suitable for different application systems; and by adjusting the depth W of each double-port system random access memory (SRAM) in an intermediate result temporary storage unit and making good compromise between the capacity of the on-chip memory and the external bandwidth, flexibility of system design is brought. Compared with the conventional 2-D convolver, the 2-D convolver occupies fewer hardware resources, the throughput can meet the real-time requirements of most image processing systems, and the 2-D convolver can be used for realizing the 2-D convolution calculation in a low-cost embedded system. The 2-D convolver belongs to the field of super-large-scale integrated circuit structure design.

Description

technical field [0001] The invention belongs to the field of VLSI (Very Large Scale Integrated Circuit) structure design, and in particular relates to a VLSI structure of a 2-D convolution device used for digital image signal processing. Background technique [0002] 2-D convolution calculation has a wide range of applications in the field of image processing, such as spatial filtering, image enhancement, template matching, etc. However, due to the large amount of multiplication-add calculations required for convolution calculations, it is difficult to achieve real-time performance with commonly used commercial DSP devices when dealing with large images or large convolution templates. Therefore, it is necessary to develop an efficient 2-D convolution VLSI structure to meet the speed and cost requirements in real-time image processing systems. [0003] The 2-D image convolution calculation is shown in formula ①. I is the image with M rows and N columns, T is the convolution ...

AI Technical Summary

Problems solved by technology

Although the traditional FB structure has the characteristics of the minimum external bandwidth, it consumes a huge amount of on-chip memory resources; SWPB requires huge external bandwidth; and MWPB reduces the on-chip memory capacity for caching image data, and the external bandwidth is relatively The increase in FB is not large, and a good compromise is achieved between hardware resource overhead and external bandwidth. However, because MWPB uses more input FIFOs, the I / O configuration becomes complicated and the number of pins increases. At the same time , the MWPB-specific output pipeline also consumes additional on-chip memory resources

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