A double silicon nanowire wrap gate field-effect transistor and its manufacture method

Abstract

The provided double-silicon nano line enclose-grid FET belonged to MOSFET technique in ULSI comprises: a silicon substrate, double silicon lines as the channels, a grid anode and multicrystal silicon grid enclosing the nano lines to form the enclose-grid structure, both source and drain connecting with the substrate, and a thick SiO2 layer between the right bottom of channel and substrate. This invention is compatible to common CMOS technique, reduces cost and power consumption, and has wide application.

Description

technical field [0001] The invention belongs to the technical field of metal oxide semiconductor field effect transistor (MetalOxide Silicon Field Effect Transistor-MOSFET) in ultra-large scale integrated circuit (ULSI), in particular to a field effect transistor surrounded by double silicon nanowires and a preparation method thereof. Background technique [0002] With the wide application and high-speed development of VLSI, MOSFET technology has entered the nanometer field (<100nm). However, when the gate length of a conventional single-gate MOSFET (which can be referred to as a device) is scaled down to sub-50nm, problems such as poor gate control capability, deterioration of short-channel effect, large leakage current, and insufficient on-state drive current will become more apparent. It's getting serious. In order to improve the gate control ability of MOSFET as much as possible, reduce the leakage current, increase the on-state drive current, increase the switching ...

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Problems solved by technology

[0003] However, the silicon nanowire multi-gate or surrounding gate devices that have been reported are either limited by the structure itself, or will bring difficulties in process preparation, etc., so that the advantages of silicon nanowire multi-gate or surrounding gate devices are often not fully reflected.

[0004] For example, the nanowire Ω gate device shown in Document 1 (F.L.Yang, D.H.Lee, H.Y. Chen, et al., "5nm-gate nanowire FinFET", in Symp.VLSl Tech.Dig, 2004, pp:196-197) (As shown in Figure 2(a)-(d)), there are the following problems: (1) it is prepared on an SOI substrate, and the cost is very high; (2) because the preparation of silicon nanowires requires a very thin top silicon film, SOI The channel on the substrate has the same thickness as the silicon film of the source and drain, as shown in Figure 2(c), which increases the parasitic series resistance of the source and drain and limits the on-state drive current; (3) at the same time, the silicon nanowire device The cross-sectional structure along the vertical direction of the channel is an Ω gate structure, as shown in Figure 2(b) and (d), which is not a surrounding gate structure, and the gate control capability needs to be further improved

[0006] However, there is still a very serious problem in the device with this structure: as shown in Figure 3 (b) and (c), there is a parasitic tube on the surface of the bulk silicon substrate directly below the double silicon nanowire, which is formed by Parasitic gate oxide, parasitic channel and shared source, drain and polysilicon gate composition

Therefore, the device with this structure shown in Document 2 has the following disadvantages: (1) The parasitic tube increases the leakage current of the entire device and reduces the switching ratio, which increases the power consumption of the device and is not suitable for low-power logic ( Low-power Logic) applications; (2) The gate capacitance of the parasitic tube also increases the total gate capacitance, which deteriorates the AC characteristics of the device and reduces the switching speed of the device, which is not suitable for high-speed logic (High-speed Logic) applications; (3) At the same time, in the process preparation, the SiGe corrosion sacrificial layer in Document 2 and the silicon channel as the nanowire are all grown epitaxially, and the process cost is still very high

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