Data transmission method and device, core particle, readable storage medium and program product

Abstract

The invention relates to a data transmission method and device, a core particle, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving first data from a consistency interconnection bus through a first receiver; the first receiver is matched with an external interface of the consistency interconnection bus; performing first conversion on the first data, and sending the converted first data to a core particle interconnection module through a first transmitter; the first transmitter is matched with the external interface of the core particle interconnection module; receiving second data from the chip particle interconnection module through a second receiver; the second receiver is matched with an external interface of the core particle interconnection module; second conversion is carried out on the second data, and the converted second data is sent to the consistency interconnection bus through the second transmitter; and the second transmitter is matched with the external interface of the consistency interconnection bus. By adopting the method, the communication between the consistency interconnection bus of the core particles and the core particle interconnection module can be realized.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and particularly to a data transmission method, apparatus, chiplet, computer-readable storage medium, and computer program product. Background Art

[0002] In the field of chip manufacturing, to enhance chip computing power, improve chip yield, and reduce costs, a large chip is split into multiple small chips (Chiplet, also known as chiplets) during chip design. The coherent interconnect buses on the chiplets usually cannot be directly interconnected, and Die To Die (DTD, chiplet interconnect module) is required to achieve off-chip interconnection between two chiplets.

[0003] In practical applications, although using DTD can solve the problem of off-chip interconnection between chiplets, due to the iterative development of products, there may be a situation where the external interface of DTD does not match the external interface of the coherent interconnect bus of the chiplet. This may cause data loss and the system to malfunction when directly connecting DTD to the coherent interconnect bus of the chiplet, resulting in data transmission failures. Summary of the Invention

[0004] Based on this, it is necessary to provide a data transmission method, apparatus, computer device, computer-readable storage medium, and computer program product that can reduce chiplet data transmission failures for the above technical problems.

[0005] In a first aspect, the present application provides a data transmission method, which is applied to a data transmission apparatus of a chiplet. A coherent interconnect bus and a chiplet interconnect module are also deployed on the chiplet. The method includes:

[0006] Receiving first data from the coherent interconnect bus via a first receiver; the first receiver is adapted to the external interface of the coherent interconnect bus;

[0007] Performing a first conversion on the first data and sending the converted first data to the chiplet interconnect module via a first transmitter; the first transmitter is adapted to the external interface of the chiplet interconnect module;

[0008] Receiving second data from the chiplet interconnect module via a second receiver; the second receiver is adapted to the external interface of the chiplet interconnect module;

[0009] Performing a second conversion on the second data and sending the converted second data to the coherent interconnect bus via a second transmitter; the second transmitter is adapted to the external interface of the coherent interconnect bus.

[0010] In one embodiment, the first conversion of the first data includes: performing cross-clock domain processing on the first data and then performing format conversion; the second conversion of the second data includes: performing format conversion on the second data and then performing cross-clock domain processing; or,

[0011] The first conversion of the first data includes: performing format conversion on the first data and then performing cross-clock domain processing; the second conversion of the second data includes: performing cross-clock domain processing on the second data and then performing format conversion.

[0012] In one embodiment, the format conversion includes at least one of protocol conversion or bit-width conversion; the protocol conversion includes at least one of adding a preset frame header or deleting a preset frame header; the bit-width conversion includes at least one of data splicing or data splitting.

[0013] In one embodiment, the method further includes: creating a first link between the die interconnect module and the coherent interconnect bus; the first link is used for transmitting second data; creating a second link between the coherent interconnect bus and the die interconnect module; the second link is used for transmitting first data.

[0014] In one embodiment, creating the first link between the die interconnect module and the coherent interconnect bus includes:

[0015] In response to a first request signal in a high level state from the die interconnect module, synchronize the first request signal in the high level state;

[0016] After the synchronization is completed, set a second request signal to a high level state; the second request signal in the high level state is used to instruct the coherent interconnect bus to set a first acknowledgment signal to a high level state;

[0017] In response to a first acknowledgment signal in a high level state from the coherent interconnect bus, synchronize the first acknowledgment signal in the high level state;

[0018] After the synchronization is completed, set a second acknowledgment signal to a high level state to complete the creation of the first link.

[0019] In one embodiment, creating the second link between the coherent interconnect bus and the die interconnect module includes:

[0020] In response to a third request signal in a high level state from the coherent interconnect bus, synchronize the third request signal in the high level state;

[0021] If synchronization is completed and a link establishment request is received from the die interconnect module, the fourth request signal is set to a high level state; the fourth request signal in the high level state is used to instruct the die interconnect module to set the third confirmation signal to a high level state;

[0022] In response to the third confirmation signal from the die interconnect module in the high level state, synchronize the third confirmation signal in the high level state;

[0023] After synchronization is completed, set the fourth confirmation signal to a high level state to complete the creation of the second link.

[0024] In one embodiment, the method further includes: disconnecting the first link between the die interconnect module and the coherence interconnect bus; the first link is the link used for the second data transmission; disconnecting the second link between the coherence interconnect bus and the die interconnect module; the second link is the link used for the first data transmission.

[0025] In one embodiment, the disconnecting the first link between the die interconnect module and the coherence interconnect bus includes:

[0026] In response to the first request signal from the die interconnect module in the low level state, synchronize the first request signal in the low level state;

[0027] After synchronization is completed, set the second request signal to a low level state; the second request signal in the low level state is used to instruct the coherence interconnect bus to set the first confirmation signal to a low level state;

[0028] In response to the first confirmation signal from the coherence interconnect bus in the low level state, synchronize the first confirmation signal in the low level state;

[0029] After synchronization is completed, set the second confirmation signal to a low level state to disconnect the first link.

[0030] In one embodiment, the disconnecting the second link between the coherence interconnect bus and the die interconnect module includes:

[0031] Set the indication signal to a high level state; the indication signal in the high level state is used to instruct the coherence interconnect bus to set the third request signal to a low level state;

[0032] In response to the third request signal from the coherence interconnect bus in the low level state, synchronize the third request signal in the low level state;

[0033] If the synchronization is completed and a disconnection request is received from the die interconnect module, the fourth request signal is set to a low level state; the fourth request signal in the low level state is used to instruct the die interconnect module to set the third confirmation signal to a low level state;

[0034] In response to the third confirmation signal from the die interconnect module in the low level state, synchronize the third confirmation signal in the low level state;

[0035] After the synchronization is completed, set the fourth confirmation signal to a low level state to disconnect the second link.

[0036] In a second aspect, the present application further provides a data transmission device, including:

[0037] A first receiver, adapted to the external interface of the coherent interconnect bus of the die, for receiving first data from the coherent interconnect bus;

[0038] A first conversion module, connected to the first receiver, for performing a first conversion on the first data received by the first receiver;

[0039] A first transmitter, connected to the first conversion module and adapted to the external interface of the die interconnect module, for sending the converted first data to the die interconnect module;

[0040] A second receiver, adapted to the external interface of the die interconnect module, for receiving second data from the die interconnect module;

[0041] A second conversion module, connected to the second receiver, for performing a second conversion on the second data received by the second receiver;

[0042] A second transmitter, connected to the second conversion module and adapted to the external interface of the coherent interconnect bus, for sending the converted second data to the coherent interconnect bus.

[0043] In one embodiment, the first conversion module includes a first format conversion unit and a first synchronization unit, the first format conversion unit is used to perform format conversion on the first data, and the first synchronization unit is used to perform cross-clock domain processing on the first data; the second conversion module includes a second format conversion unit and a second synchronization unit, the second format conversion unit is used to perform format conversion on the second data, and the second synchronization unit is used to perform cross-clock domain processing on the second data.

[0044] In one embodiment, the device further includes an extraction module, which is respectively connected to the second receiver and the first transmitter, and is configured to identify whether the data signal sent by the die interconnect module includes a link establishment request or a link disconnection request.

[0045] In a third aspect, the present application further provides a die, including a coherent interconnect bus, a data transmission device, a die interconnect module, a memory, and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above data transmission method are implemented.

[0046] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above data transmission method are implemented.

[0047] In a fifth aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the above data transmission method are implemented.

[0048] The above data transmission method, device, die, computer-readable storage medium, and computer program product realize an asynchronous interface connection between the coherent interconnect bus of the die and the die interconnect module through a set of interfaces (i.e., the first receiver and the second transmitter) that dock with the coherent interconnect bus of the die, and a set of interfaces (i.e., the first transmitter and the second receiver) that dock with the die interconnect module (DTD), enabling normal data reception and transmission. Through data conversion during the transmission process, the data can be correctly transmitted, ensuring the normal operation of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 It is an application environment diagram of the data transmission method in an embodiment;

[0051] Figure 2 It is a structural block diagram of the data transmission device in an embodiment;

[0052] Figure 3 It is a structural block diagram of the data transmission device in another embodiment;

[0053] Figure 4 It is a structural block diagram of the data transmission device in yet another embodiment;

[0054] Figure 5 It is a communication architecture diagram of the die interconnect module and the coherent interconnect bus in an embodiment;

[0055] Figure 6 It is a schematic flowchart of a data transmission method in an embodiment;

[0056] Figure 7 It is a schematic flowchart of the link establishment process in an embodiment;

[0057] Figure 8 It is a schematic flowchart of the link disconnection process in an embodiment.

[0058] Description of the reference numerals:

[0059] 10 - die, 12 - coherent interconnect bus, 14 - die interconnect module, 16 - data transmission device, 161 - first receiver, 162 - first conversion module, 163 - first transmitter, 164 - second receiver, 165 - second conversion module, 166 - second transmitter, 167 - extraction module, 1621 - first format conversion unit, 1622 - first synchronization unit, 1651 - second format conversion unit, 1652 - second synchronization unit. Detailed implementation manners

[0060] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] It should be noted that the terms "first", "second", etc. mentioned in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element and are not used to define the order. For example, without departing from the scope of the present application, the first receiver can be called the second receiver, and similarly, the first transmitter can be called the second transmitter, etc.

[0062] In the field of chip manufacturing, to enhance chip computing power, improve chip yield, and reduce costs, a large chip is split into multiple chiplets during chip design. Different chiplets usually need to be interconnected using Die To Die (DTD or D2D, chiplet interconnection module) to achieve communication between chiplets. In practical applications, there may be a situation where the external interface of the DTD is inconsistent with the external interface of the chiplet's coherent mesh network (CMN, also known as coherent interconnection network or coherent mesh network). For example, the external interfaces of the DTD and the coherent interconnection bus correspond to different interface protocols, or different versions of the same interface protocol, resulting in the inability to directly connect and communicate between the DTD and the coherent interconnection bus. Exemplarily, in some cases, the external interface of the DTD is the CXS.B interface, while the external interface of the chiplet's coherent interconnection bus, such as CMN600AE, is the CXS.A interface. If CMN600AE and the DTD are directly connected, it will lead to situations where data cannot be recognized, data is lost, and the system cannot work properly. Among them, CXS is Credited eXtensibleStream, a stream interface protocol for point-to-point packet communication. CXS.A is version A of the stream interface protocol, and CXS.B is version B of the stream interface protocol.

[0063] In view of this, the embodiments of the present application provide a data transmission method. Through a set of interfaces that dock with the chiplet's coherent interconnection bus and a set of interfaces that dock with the chiplet interconnection module (DTD), an asynchronous interface connection between the chiplet's coherent interconnection bus and the chiplet interconnection module is achieved, enabling normal data reception and transmission. Then, through data conversion during the transmission process, the data can be correctly transmitted, ensuring the normal operation of the chip system.

[0064] Before introducing the data transmission device and data transmission method provided by the present application in detail, the application environment to which the data transmission device and data transmission method are applied will be described first. In an exemplary embodiment, the data transmission device and / or method can be applied to, for example Figure 1In the application environment shown below, a single die will be taken as an example for illustration. On the die 10, a coherent interconnect bus 12 and a die interconnect module DTD 14 are deployed. Through the data transmission device 16, normal communication (data transmission) between the coherent interconnect bus 12 and the die interconnect module DTD 14 can be achieved. The die interconnect module DTD 14 deployed on the die 10 can perform data transmission with the die interconnect modules DTD deployed on other dies to realize communication and interconnection between different dies. The structures of other dies can be the same as or different from that of the die 10, which is not limited in the embodiments of the present application. It should be noted that the data transmission device 16 in the present application can be implemented by an asynchronous bridge, and the asynchronous bridge can also be deployed on the die 10. In some embodiments, the asynchronous bridge can specifically be an asynchronous bridge of the stream interface protocol (CXS bridge).

[0065] In an exemplary embodiment, as Figure 2 shown, the data transmission device 16 includes: a first receiver 161, adapted to the external interface of the coherent interconnect bus 12, for receiving the first data from the coherent interconnect bus 12; a first conversion module 162, connected to the first receiver 161, for performing a first conversion on the first data received by the first receiver 161; a first transmitter 163, connected to the first conversion module 162 and adapted to the external interface of the die interconnect module 14, for sending the converted first data to the die interconnect module 14; a second receiver 164, adapted to the external interface of the die interconnect module 14, for receiving the second data from the die interconnect module 14; a second conversion module 165, connected to the second receiver 164, for performing a second conversion on the second data received by the second receiver 164; a second transmitter 166, connected to the second conversion module 165 and adapted to the external interface of the coherent interconnect bus 12, for sending the converted second data to the coherent interconnect bus 12.

[0066] As mentioned above, to achieve data communication between different dies, data transmission is required between the coherent interconnect bus 12 and the die interconnect module (DTD) 14 deployed on a single die. Since the coherent interconnect bus 12 and the die interconnect module (DTD) 14 may respectively correspond to different interface protocols, or different versions of the same interface protocol, it will cause the inability to directly connect between the coherent interconnect bus 12 and the die interconnect module 14. For example, the external interface of the DTD is the CXS.B interface, while the external interface of the coherent interconnect bus of the die, such as CMN600AE, is the CXS.A interface.

[0067] Therefore, this application designs two sets of interfaces to be respectively connected to the chiplet interconnection module 14 and the coherence interconnection bus 12. Any one of the interfaces consists of a Receiver (RX) and a Transmitter (TX). Specifically, one set of interfaces consists of a second transmitter 166 and a first receiver 161, which is adapted to the interface protocol and protocol version corresponding to the external interface of the coherence interconnection bus 12 for docking with the coherence interconnection bus 12; the other set of interfaces consists of a first transmitter 163 and a second receiver 164, which is adapted to the interface protocol and protocol version corresponding to the external interface of the chiplet interconnection module 14 for docking with the chiplet interconnection module 14.

[0068] Specifically, the first receiver 161 can receive the first data from the coherence interconnection bus 12. The first conversion module 162 connected to the first receiver 161 performs a first conversion on the first data to convert the first data into data that the chiplet interconnection module 14 can process. Then, the first transmitter 163 sends the converted first data to the chiplet interconnection module 14 to achieve data transmission from the coherence interconnection bus 12 to the chiplet interconnection module 14. It can be understood that the first receiver 161 is adapted to the external interface of the coherence interconnection bus 12 (i.e., corresponding to the same interface protocol and protocol version) so as to be able to successfully receive the first data from the coherence interconnection bus 12; the first transmitter 163 is adapted to the external interface of the chiplet interconnection module 14 (i.e., corresponding to the same interface protocol and protocol version) so as to be able to successfully send the converted first data to the chiplet interconnection module 14.

[0069] Similarly, to achieve data transmission from the chiplet interconnection module 14 to the coherence interconnection bus 12 of the chiplet, the data transmission device 16 in this application is also designed with a second receiver 164, a second conversion module 165, and a second transmitter 166. Among them, the second receiver 164 can receive the second data from the chiplet interconnection module 14. The second conversion module 165 performs a second conversion on the second data to convert the second data into data that the coherence interconnection bus 12 can process. Then, the second transmitter 166 sends the converted second data to the coherence interconnection bus 12 to achieve data transmission from the chiplet interconnection module 14 to the coherence interconnection bus 12. It can be understood that the second receiver 164 is adapted to the external interface of the chiplet interconnection module 14 (i.e., corresponding to the same interface protocol and protocol version) so as to be able to successfully receive the second data from the chiplet interconnection module 14; the second transmitter 166 is adapted to the external interface of the coherence interconnection bus 12 (i.e., corresponding to the same interface protocol and protocol version) so as to be able to successfully send the converted second data to the coherence interconnection bus 12.

[0070] It should be noted that the first data transmitted by the coherent interconnect bus 12 of the chiplet can be instructions, calculation results, intermediate cache data, etc. generated by the chiplet; the second data transmitted by the chiplet interconnect module 14 can specifically come from other chiplets, such as instructions, calculation results, intermediate cache data, etc. generated by other chiplets.

[0071] The above data transmission device realizes the asynchronous interface connection between the coherent interconnect bus of the chiplet and the chiplet interconnect module through a set of interfaces docked with the coherent interconnect bus of the chiplet and a set of interfaces docked with the chiplet interconnect module (DTD), enabling the normal reception and transmission of data. Then, through data conversion during the transmission process, the data can be correctly transmitted, ensuring the normal operation of the chip system.

[0072] Reference Figure 3 , in some embodiments, the first conversion module 162 includes a first format conversion unit 1621 and a first synchronization unit 1622. The first format conversion unit 1621 is used to perform format conversion on the first data, and the first synchronization unit 1622 is used to perform cross-clock domain processing on the first data; the second conversion module 165 includes a second format conversion unit 1651 and a second synchronization unit 1652. The second format conversion unit 1651 is used to perform format conversion on the second data, and the second synchronization unit 1652 is used to perform cross-clock domain processing on the second data.

[0073] It should be noted that the chiplet interconnect module 14 and the coherent interconnect bus 12 of the chiplet are usually driven by different clocks and are usually in different clock domains. Therefore, when the data transmission device 16 performs data transmission, cross-clock domain processing is usually required to convert the data in the first clock domain to the second clock domain, or convert the data in the second clock domain to the first clock domain. In addition, since the communication protocols supported by the chiplet interconnect module 14 and the coherent interconnect bus 12 of the chiplet are different, data format conversion is also required during data transmission.

[0074] In some embodiments, if the coherent interconnect bus 12 and the chiplet interconnect module 14 are in the same clock domain, the first conversion module 162 may include the first format conversion unit 1621 but not the first synchronization unit 1622, and the second conversion module 165 may include the second format conversion unit 1651 but not the second synchronization unit 1652.

[0075] In some embodiments, the first receiver 161, the first format conversion unit 1621, the first synchronization unit 1622, and the first transmitter 163 are connected in sequence, and the second receiver 164, the second synchronization unit 1652, the second format conversion unit 1651, and the second transmitter 166 are connected in sequence. In other embodiments, the first receiver 161, the first synchronization unit 1622, the first format conversion unit 1621, and the first transmitter 163 are connected in sequence, and the second receiver 164, the second format conversion unit 1651, the second synchronization unit 1652, and the second transmitter 166 are connected in sequence.

[0076] In some embodiments, the first format conversion unit 1621 is configured to perform at least one of protocol conversion or bit-width conversion, and the second format conversion unit 1651 performs at least one of protocol conversion or bit-width conversion. Moreover, the protocol conversion performed by the first format conversion unit 1621 and the protocol conversion performed by the second format conversion unit 1651 are inverse processes of each other, and the bit-width conversion performed by the first format conversion unit 1621 and the bit-width conversion performed by the second format conversion unit 1651 are inverse processes of each other.

[0077] Specifically, the protocol conversion performed by the first format conversion unit 1621 may specifically include adding a preset frame header, and the bit-width conversion performed may specifically include one of data splicing and data splitting. Correspondingly, the protocol conversion performed by the second format conversion unit 1651 may specifically include deleting a preset frame header, and the bit-width conversion performed may specifically include the other of data splicing and data splitting.

[0078] It can be understood that when the data bit-width corresponding to the external interface of the coherent interconnect bus 12 is 1 / n (n is an integer greater than 1) of the data bit-width of the external interface of the die interconnect module 14, the bit-width conversion performed by the first format conversion unit 1621 may specifically be splicing n data packets into one data packet (i.e., data splicing), and the bit-width conversion performed by the second format conversion unit 1651 may specifically be splitting one data packet into n data packets (i.e., data splitting). Conversely, when the data bit-width corresponding to the external interface of the coherent interconnect bus 12 is n times the data bit-width of the external interface of the die interconnect module 14, the bit-width conversion performed by the first format conversion unit 1621 may specifically be splitting 1 data packet into n data packets (i.e., data splitting), and the bit-width conversion performed by the second format conversion unit 1651 may specifically be splicing n data packets into one data packet (i.e., data merging).

[0079] In the above embodiments, for the data transmission process from the coherent interconnect bus to the die interconnect module, a first synchronization unit and a first format conversion unit are designed, which can convert the frequency domain and data format corresponding to the first data to match its counterpart, so that the die interconnect module can correctly parse the data; for the data transmission process from the die interconnect module to the coherent interconnect bus, a second synchronization unit and a second format conversion unit are designed, which can convert the frequency domain and data format corresponding to the second data to match its counterpart, so that the coherent interconnect bus can correctly parse the data. Thus, the data transmission between the coherent interconnect bus and the die interconnect module is realized.

[0080] Referring Figure 4 , in some embodiments, the data transmission device 16 further includes an extraction module 167, which is respectively connected to the second receiver 164 and the first transmitter 163, and is used to identify whether the data signal sent by the die interconnect module 14 includes a link establishment request or a link disconnection request.

[0081] Among them, the extraction module 167 is used to parse the specific link establishment information and link disconnection information sent by the die interconnect module 14 to help establish and disconnect the communication link between the die interconnect module and the coherent interconnect bus. For the relevant content of the extraction module 167 to identify whether the data signal includes a link establishment request or a link disconnection request, please refer to the following descriptions of the link establishment process and the link disconnection process.

[0082] In one embodiment, the data transmission device 16 may specifically include:

[0083] A first receiver 161, adapted to the external interface of the coherent interconnect bus 12 of the die, for receiving the first data from the coherent interconnect bus 12.

[0084] A first format conversion unit 1621, connected to the first receiver 161, for performing format conversion on the first data; exemplarily, the first format conversion unit 1621 may specifically be used to splice the first data and then add a preset frame header, or add a preset frame header to the first data and then perform data splicing, or split the first data and then add a preset frame header.

[0085] A first synchronization unit 1622, connected to the first format conversion unit 1621, for performing cross-clock domain processing on the first data after the first format conversion.

[0086] A first transmitter 163, connected to the first synchronization unit 1622 and adapted to the external interface of the die interconnect module 14, for sending the first data after the first format conversion and cross-clock domain processing to the die interconnect module 14.

[0087] The second receiver 164 is adapted to the external interface of the chip-grain interconnect module 14 and is used to receive the second data from the chip-grain interconnect module 14 .

[0088] The second synchronization unit 1652 is connected to the second receiver 164 and is used for performing cross-clock domain processing on the second data.

[0089] The second format conversion unit 1651 is connected to the second synchronization unit 1652, and is used for format conversion of the second data after cross-clock domain processing; exemplarily, the second format conversion unit 1651 can be specifically used to delete the preset frame header of the second data after cross-clock domain processing and then perform data splitting, or to delete the preset frame header after data splitting, or to delete the preset frame header of the second data after cross-clock domain processing and then perform data splicing.

[0090] The second transmitter 166 is connected to the second format conversion unit 1651 and adapted to the external interface of the coherent interconnect bus 12 , and is used for sending the second data after cross-clock domain processing and format conversion to the coherent interconnect bus 12 .

[0091] The extraction module 167 is connected to the second receiver 164 and the first transmitter 163 respectively, and is used to identify whether the data signal sent by the core-grain interconnect module 14 includes a link establishment request during the process of creating a communication link between the consistent interconnect bus 12 and the core-grain interconnect module 14, and is also used to identify whether the data signal sent by the core-grain interconnect module 14 includes a link disconnection request during the process of disconnecting the communication link between the consistent interconnect bus 12 and the core-grain interconnect module 14.

[0092] In a specific embodiment, the consistent interconnect bus is CMN600AE, the external interface of the consistent interconnect bus corresponds to the A version of the CXS protocol (ie, CXS.A), and supports the data transmission of the CCIX1.0 (where CCIX is Cache Coherent Interconnect for Accelerators, a high-performance interconnect protocol); the external interface of the core grain interconnect module DTD corresponds to the B version of the CXS protocol (ie, CXS.B), and supports the data transmission of the CXL2.0 / CCIX2.0 (where CXL is Compute Express Link, an open interconnect protocol) protocol as an example, the communication architecture of the core grain interconnect module and the consistent interconnect bus is described:

[0093] like Figure 5 As shown, the data transmission device of the present application (such as Figure 5The CXS_Asynchronous Bridge shown in the figure (also known as CXS A2CXS B_Bridge), where there are two sets of CXS interfaces respectively interconnected with CMN600AE and DTD. Two asynchronous FIFOs (First In First Out buffers) are used for cross-clock domain processing to synchronize data. Among them, the tx_asynchronous FIFO is the first synchronization unit mentioned above, and the rx_asynchronous FIFO is the second synchronization unit mentioned above. For the tx_asynchronous FIFO and rx_asynchronous FIFO, they are represented by splicing two different colors (blue and green) in Figure 5 Both are represented by splicing two different colors (blue and green), where different colors represent two different frequency domains. Packing (pack, which is the first format conversion unit mentioned above) and unpacking (unpack, which is the second format conversion unit mentioned above) are used for protocol conversion and bit width conversion between CCIX1.0 and CCIX2.0. The extraction module (also known as LLCTRL_EXTRACT) is used to parse the specific link establishment and disconnection information of DTD. The data bit width of CXS.A is 256 bits, and the data bit width of CXS.B is 512 bits. After CMN600AE sends data to the asynchronous bridge using the CXS.A interface, the asynchronous bridge will add a specific frame header to the data to implement protocol conversion, and then splice two 256-bit CXS.A data into a 512-bit CXS.B data, improving the bandwidth utilization rate. Since CMN600AE and DTD are asynchronously designed, the tx_asynchronous FIFO is used for synchronization, and then the converted data is sent to DTD using the CXS.B interface; when DTD sends data to CMN600AE, after the asynchronous bridge receives the data sent by DTD, it is processed by the rx_asynchronous FIFO, and then the unpacking unit restores and sends the data to CMN600AE. In this way, the data transmission between DTD and CMN600AE is realized.

[0094] It should be noted that each module in the above data transmission device can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0095] Next, the data transmission method applied to the above data transmission device 16 will be described in detail:

[0096] In an exemplary embodiment, as Figure 6 shown, a data transmission method is provided, which includes the following steps 602 to step 608. Among them:

[0097] Step 602: Receive first data from the coherent interconnect bus via a first receiver; the first receiver is adapted to the interface of the coherent interconnect bus.

[0098] Among them, the first receiver 161 is one of the interfaces in a set of interfaces of the data transmission device, and is used to receive the first data from the coherent interconnect bus 12. It can be understood that the first receiver 161 is adapted to the external interface of the coherent interconnect bus 12 (that is, corresponding to the same interface protocol and protocol version) so as to be able to successfully receive the first data from the coherent interconnect bus 12.

[0099] Step 604: Perform a first conversion on the first data, and send the converted first data to the die interconnect module via a first transmitter; the first transmitter is adapted to the external interface of the die interconnect module.

[0100] Specifically, the first conversion module 162 can perform a first conversion on the first data received by the first receiver 161, and then send the converted first data to the die interconnect module 14 through the first transmitter 163 to realize data transmission from the coherent interconnect bus 12 to the die interconnect module 14. It can be understood that the first transmitter 163 is adapted to the external interface of the die interconnect module 14 (that is, corresponding to the same interface protocol and protocol version) so as to be able to successfully send the converted first data to the die interconnect module 14.

[0101] In some embodiments, the coherent interconnect bus 12 and the die interconnect module 14 are driven by different clocks and operate at different clock frequencies, or even if the frequencies are the same, the phases may be different. Therefore, data transmission between different clock domains involves cross-clock domain processing, that is, this first conversion may specifically include cross-clock domain processing. Exemplarily, the cross-clock domain processing may include asynchronous FIFO processing. Among them, FIFO is a first-in-first-out queue structure, which can provide data buffering and synchronization functions between different clock domains. Asynchronous FIFO processing specifically controls data to be written into the FIFO buffer from one clock domain and read from the same FIFO buffer from another clock domain, and the two clock domains are asynchronous to each other. Asynchronous FIFO processing is used to safely transfer data from one clock domain to another clock domain.

[0102] In some embodiments, the coherent interconnect bus 12 and the die interconnect module 14 respectively support different data transmission protocols. For example, the coherent interconnect bus CMN600AE supports the CCIX1.0 protocol, while DTD supports the CXL2.0 / CCIX2.0 protocol. Therefore, this first conversion may specifically include protocol conversion.

[0103] In some embodiments, the data bit widths of the coherent interconnect bus 12 and the die interconnect module 14 do not match. For example, the data bit width of CXS.A is 256 bits, and the data bit width of CXS.B is 512 bits. Therefore, this first conversion may include bit width conversion.

[0104] In some embodiments, the first conversion may include at least one of cross-clock domain processing, protocol conversion, or bit width conversion.

[0105] Step 606, receive second data from the die interconnect module via a second receiver; the second receiver is adapted to the external interface of the die interconnect module.

[0106] Similarly, to implement data transmission from the die interconnect module (DTD) 14 to the coherent interconnect bus 12 of the die, the data transmission device 16 in this application is also designed with a second receiver 164 that is adapted to the interface of the die interconnect module (DTD) 14 (i.e., corresponding to the same interface protocol and protocol version) to receive the second data transmitted by the die interconnect module (DTD) 14.

[0107] Step 608, perform a second conversion on the second data, and send the converted second data to the coherent interconnect bus via a second transmitter; the second transmitter is adapted to the external interface of the coherent interconnect bus.

[0108] The second conversion module 165 in the data transmission device 16 can perform a second conversion on the second data, and then send the converted second data to the coherent interconnect bus 12 through the second transmitter 166 in the data transmission device 16 to implement data transmission from the die interconnect module 14 to the coherent interconnect bus 12. It can be understood that the second transmitter 166 is adapted to the external interface of the coherent interconnect bus 12 (i.e., corresponding to the same interface protocol and protocol version) so as to be able to successfully send the converted second data to the coherent interconnect bus 12.

[0109] In some embodiments, the coherent interconnect bus 12 and the die interconnect module 14 are driven by different clocks and have different frequencies. Therefore, this second conversion may specifically include cross-clock domain processing to perform asynchronous FIFO processing on the data.

[0110] In some embodiments, the coherent interconnect bus 12 and the die interconnect module 14 respectively support different data transmission protocols. For example, the coherent interconnect bus CMN600AE supports the CCIX1.0 protocol, while the DTD supports the CXL2.0 / CCIX2.0 protocol. Therefore, this second conversion may specifically include protocol conversion.

[0111] In some embodiments, the data bit widths corresponding to the coherent interconnect bus 12 and the die interconnect module 14 are inconsistent. For example, the data bit width of CXS.A is 256 bits, and the data bit width of CXS.B is 512 bits. Therefore, the second conversion may include bit width conversion.

[0112] In some embodiments, the second conversion may include at least one of cross-clock domain processing, protocol conversion, or bit width conversion. It can be understood that the first conversion and the second conversion are inverse processes of each other.

[0113] In addition, it should be noted that this application does not limit the transmission timing of the first data and the second data, that is, the order between the above steps 602 to 604 and the above steps 606 to 608 is not limited. It may be to first execute steps 602 to 604 and then execute steps 606 to 608; or, first execute steps 606 to 608 and then execute steps 602 to 604; or, while executing steps 602 to 604, execute steps 606 to 608.

[0114] The above data transmission method realizes the asynchronous interface connection between the coherent interconnect bus of the die and the die interconnect module through a set of interfaces docked with the coherent interconnect bus of the die and a set of interfaces docked with the die interconnect module (DTD), enabling the normal reception and transmission of data. Then, through the data conversion during the transmission process, the data can be correctly transmitted, ensuring the normal operation of the chip system.

[0115] In some embodiments, performing the first conversion on the first data includes: performing cross-clock domain processing on the first data and then performing format conversion; performing the second conversion on the second data includes: performing format conversion on the second data and then performing cross-clock domain processing; or, performing the first conversion on the first data includes: performing format conversion on the first data and then performing cross-clock domain processing; performing the second conversion on the second data includes: performing cross-clock domain processing on the second data and then performing format conversion.

[0116] Specifically, the steps of format conversion can be performed on the side with a higher frequency to improve data processing efficiency. For example, if the frequency corresponding to the coherent interconnect bus 12 of the die is lower than the frequency of the die interconnect module (DTD) 14, the first conversion of the first data includes: performing cross-clock domain processing on the first data and then performing format conversion to obtain the converted first data; the second conversion of the second data includes: performing format conversion on the second data and then performing cross-clock domain processing to obtain the converted second data. If the frequency corresponding to the coherent interconnect bus of the die is higher than the frequency of the die interconnect module (DTD), the first conversion of the first data includes: performing format conversion on the first data and then performing cross-clock domain processing to obtain the converted first data; the second conversion of the second data includes: performing cross-clock domain processing on the second data and then performing format conversion to obtain the converted second data.

[0117] In some embodiments, if the coherent interconnect bus 12 of the die and the die interconnect module (DTD) 14 are in the same clock domain, that is, they correspond to the same frequency, then cross-clock domain processing may not be included in the first conversion and / or the second conversion.

[0118] In some embodiments, format conversion includes at least one of protocol conversion or bit-width conversion; protocol conversion includes at least one of adding a preset frame header or deleting a preset frame header; bit-width conversion includes at least one of data splicing or data splitting.

[0119] Exemplarily, when performing protocol conversion on the first data, it may specifically be adding a preset frame header, and when performing protocol conversion on the second data, it may specifically be deleting a preset frame header. That is, the protocol conversions of the first data and the second data are inverse processes. It should be noted that the purpose of adding a preset frame header to the data is to make the converted data conform to the protocol corresponding to the data receiver. For example, when the CMN600AE uses the CXS.A interface to send data to the data transmission device, the first format conversion unit 1621 of the data transmission device 16 adds a specific frame header (i.e., the frame header of the data transmission protocol supported by the die conversion module) to the data to achieve protocol conversion.

[0120] Exemplarily, when performing bit-width conversion on the first data, data splicing can be specifically performed. When performing bit-width conversion on the second data, data splitting can be specifically performed. Conversely, when performing bit-width conversion on the first data, data splitting can be specifically performed. When performing bit-width conversion on the second data, data splicing can be specifically performed. That is to say, the bit-width conversions of the first data and the second data are inverse processes of each other. It should be noted that the purpose of data splicing is to improve the bandwidth utilization rate during data transmission. For example, the data bit-width of CXS.A is 256 bits, and the data bit-width of CXS.B is 512 bits. The data transmission device can splice two 256-bit CXS.A data into a 512-bit CXS.B data for transmission, improving the bandwidth utilization rate.

[0121] In this way, at least one format conversion of protocol conversion or bit-width conversion is performed on the transmitted data during data transmission, so that the converted data can be parsed by the data receiver, ensuring the normal operation of the system.

[0122] In some embodiments, there are at least the following situations for performing format conversion on the first data and performing format conversion on the second data:

[0123] Situation 1: The data transmission protocols supported by the coherent interconnect bus 12 and the die interconnect module 14 are different, and the data bit-width corresponding to the external interface of the coherent interconnect bus 12 is smaller than the data bit-width corresponding to the external interface of the die interconnect module 14. In this case, the format conversion of the first data and the second data can specifically be: adding a preset frame header to the first data and then performing packet combining processing (i.e., data splicing), and performing packet splitting processing (i.e., data splitting) on the second data and then deleting the preset frame headers in the obtained multiple data respectively. Or, performing packet combining processing on the first data and then adding a preset frame header, and deleting the preset frame header in the second data and then performing packet splitting processing on the second data.

[0124] Situation 2: The data transmission protocols supported by the coherent interconnect bus 12 and the die interconnect module 14 are different, and the data bit-width corresponding to the external interface of the coherent interconnect bus 12 is larger than the data bit-width corresponding to the external interface of the die interconnect module 14. In this case, the format conversion of the first data and the second data can specifically be: performing packet splitting processing on the first data and then adding a preset frame header to each of the obtained multiple data, and deleting the preset frame headers in the multiple second data and then performing packet combining processing on the second data.

[0125] In the above embodiments, during the transmission of the first data and / or the second data, format conversion and cross-clock domain processing are performed, so that the format and clock domain of the converted data can match the data receiver, avoiding the situation that the data receiver cannot parse the data or has a data reception failure, and enabling both the coherent interconnect bus and the die interconnect module to work properly.

[0126] In some embodiments, before the coherent interconnect bus 12 of the die transmits data to the die interconnect module (DTD) 14, a communication link between the die interconnect module 14 and the coherent interconnect bus 12 needs to be established first. The link includes a first link and a second link to ensure that data transmission can be achieved subsequently. That is, the data transmission method may further include a link establishment process, which may specifically include the following steps: creating a first link between the die interconnect module 14 and the coherent interconnect bus 12; the first link is used for the transmission of the second data; creating a second link between the coherent interconnect bus 12 and the die interconnect module 14; the second link is used for the transmission of the first data.

[0127] It can be understood that after the first link and the second link are successfully created, the smooth transmission of the first data and the second data can be achieved, enabling the successful interconnection of the coherent interconnect bus 12 of the die and the die interconnect module 14.

[0128] The following will be combined with Figure 7 to elaborate in detail on the creation process of the first link and the second link:

[0129] In some embodiments, creating a first link between the die interconnect module 14 and the coherent interconnect bus 12 includes: synchronizing a first request signal in a high-level state in response to a first request signal in a high-level state from the die interconnect module 14; after the synchronization is completed, setting a second request signal in a high-level state; the second request signal in a high-level state is used to instruct the coherent interconnect bus 12 to set a first acknowledgment signal in a high-level state; synchronizing a first acknowledgment signal in a high-level state in response to a first acknowledgment signal in a high-level state from the coherent interconnect bus 12; after the synchronization is completed, setting a second acknowledgment signal in a high-level state to complete the creation of the first link.

[0130] In some embodiments, when different core interconnect modules enter operation, they will be connected to each other. When any core interconnect module is successfully connected to other core interconnect modules, the core interconnect module can pull up the first request signal, that is, put the first request signal in a high level state (such as logic "1") to wake up the second receiver 164. In this way, when the data transmission device 16 detects that the first request signal is in a high level state, it will synchronize the first request signal in a high level state. After the synchronization is completed, the first request synchronization signal is placed in a high level state. When the data transmission device 16 detects that the first request synchronization signal is in a high level state, it pulls up the second request signal (that is, the second request signal is placed in a high level state). In response to the second request signal in a high level state, the core consistency interconnect bus 12 pulls up the first confirmation signal. The data transmission device 16 synchronizes the first confirmation signal in a high level state, and puts the first confirmation synchronization signal in a high level state after the synchronization is completed. After the data transmission device 16 detects the first confirmation synchronization signal in a high level state, it pulls up the second confirmation signal. At this point, the first link is successfully established.

[0131] The synchronization of the signal may specifically be cross-clock domain processing, converting the frequency of the signal to a frequency that matches the data receiver. It may be cross-clock domain processing using the same module as above, or it may be processed by a different module, which is not limited in the present embodiment.

[0132] In the above embodiment, by pulling up the relevant signal, the request process from DTD to the consistent interconnect bus and the confirmation process from the consistent interconnect bus to DTD can be realized to create a first link, so that the first data can be transmitted through the first link.

[0133] In some embodiments, creating a second link between the consistent interconnect bus 12 and the chip interconnect module 14 includes: responding to a third request signal in a high state from the consistent interconnect bus 12, synchronizing the third request signal in a high state; if the synchronization is completed and a link establishment request is received from the chip interconnect module 14, setting the fourth request signal to a high state; the fourth request signal in a high state is used to instruct the chip interconnect module 14 to set the third confirmation signal to a high state; responding to the third confirmation signal in a high state from the chip interconnect module 14, synchronizing the third confirmation signal in a high state; after the synchronization is completed, setting the fourth confirmation signal to a high state to complete the creation of the second link.

[0134] After the first link is successfully established, the core-grain interconnection module 14 can transmit a link establishment request through a data signal. For the data transmission device 16, after receiving the data signal transmitted by the core-grain interconnection module 14, it will analyze the data signal, and if the data in the data signal meets the preset link establishment rule, it is determined that the link establishment request is received. The data in the data signal meets the preset link establishment rule, for example, the value of the preset bit in the data signal is 1.

[0135] If the data transmission device 16 receives the third request signal in a high level state transmitted from the consistency interconnect bus 12, the third request signal in a high level state is synchronized. If the synchronization is completed, the third request synchronization signal is set to a high level state. If the data transmission device 16 detects that the third request synchronization signal is in a high level state and receives the link establishment request transmitted by the core grain interconnect module 14, the fourth request signal is pulled high. Then the core grain interconnect module 14 can pull up the third confirmation signal, so that the data transmission device 16 synchronizes the third confirmation signal. After the synchronization is completed, the third confirmation synchronization signal is set to a high level state. If the data transmission device 16 detects that the third confirmation synchronization signal is in a high level state, the fourth confirmation signal is set to a high level state. At this point, the second link is also successfully established.

[0136] In the above embodiment, by pulling up the relevant signal, the request process from the consistent interconnect bus to the DTD and the confirmation process from the DTD to the consistent interconnect bus can be realized to create a second link, so that the second data can be transmitted through the second link.

[0137] Specifically, please refer to Figure 7 , Figure 7 The process of establishing a first link and a second link in an embodiment specifically includes the following steps:

[0138] 1) DTD pulls the first request signal CXSB.RXREQ high to wake up the CXS.B interface (ie, the second receiver), and synchronizes the first request signal CXSB.RXREQ signal, but does not pull the second confirmation signal CXSB.RXACK high.

[0139] 2) After receiving the synchronized first request synchronization signal CXSB.RXREQ_SYNC, the asynchronous bridge pulls up the second request signal CXSA.TXREQ.

[0140] 3) CMN pulls up the first confirmation signal CXSA.TXACK in response and synchronizes the first confirmation signal CXSA.TXACK at the same time.

[0141] 4) After the asynchronous bridge receives the first confirmation synchronization signal CXSA.TXACK_SYNC after synchronization, it pulls up the second confirmation signal CXSB.RXACK. At this point, the following link is successfully established.

[0142] 5) DTD transmits the link establishment request through the data signal CXSB.DATA, and pulls the module LLCTRL to let the asynchronous bridge initiate the link establishment request.

[0143] 6) CMN pulls up the third request signal CXSA.RXREQ and synchronizes the third request signal CXSA.RXREQ.

[0144] 7) When the third request synchronization signal CXSA.RXREQ_SYNC is detected and a link establishment request is received, the asynchronous bridge pulls up the fourth request signal CXSB.TXREQ.

[0145] 8) DTD pulls up the third confirmation signal CXSB.TXACK in response and synchronizes the third confirmation signal CXSB.TXACK at the same time.

[0146] 9) After the asynchronous bridge receives the third confirmation synchronization signal CXSB.TXACK_SYNC after synchronization, it pulls up the fourth confirmation signal CXSA.RXACK. At this point, the above link is also successfully established.

[0147] It should be noted that the sending and receiving of relevant signals in the asynchronous bridge are both realized through corresponding transmitters and receivers.

[0148] After the first link and the second link are successfully created, data can be transmitted between the chiplet's consistent interconnect bus 12 and the chiplet interconnect module 14 through the first link and the second link, thereby realizing data transmission between different chiplets. If the link breaking condition is met, the first link and the second link will be disconnected to save resources. Among them, the link breaking condition can specifically be that the chiplet interconnect module (DTD) 14 fails, or that no data is transmitted between the chiplet's consistent interconnect bus 12 and the chiplet interconnect module 14 within a preset time.

[0149] In some embodiments, the data transmission method may also include a link breaking process, that is, including the following steps: disconnecting the first link between the chip interconnect module 14 and the consistent interconnect bus 12; the first link is the link used for the first data transmission; disconnecting the second link between the consistent interconnect bus 12 and the chip interconnect module 14; the second link is the link used for the second data transmission.

[0150] It can be understood that after the first link is disconnected from the second link, the chiplet coherent interconnect bus 12 and the chiplet interconnect module 14 cannot communicate with each other, which can reduce resource consumption in some cases.

[0151] The following will elaborate in detail on the disconnection process of the first link and the disconnection process of the second link in conjunction with Figure 8 :

[0152] In some embodiments, disconnecting the first link between the D2D module and the interconnect bus includes: synchronizing a first request signal in a low level state in response to the first request signal in a low level state from the chiplet interconnect module 14; after the synchronization is completed, setting the second request signal to a low level state; the second request signal in a low level state is used to instruct the coherent interconnect bus 12 to set the first acknowledgment signal to a low level state; synchronizing the first acknowledgment signal in a low level state in response to the first acknowledgment signal in a low level state from the coherent interconnect bus 12; after the synchronization is completed, setting the second acknowledgment signal to a low level state to disconnect the first link.

[0153] In some embodiments, when disconnection is required, the chiplet interconnect module 14 can pull down the first request signal, that is, set the first request signal to a low level state (such as logic "0"). In this way, when the data transmission device 16 detects that the first request signal is in a low level state, it will synchronize the first request signal in a low level state. After the synchronization is completed, the second request signal is pulled down (that is, the second request signal is set to a low level state). In response to the second request signal in a low level state, the coherent interconnect bus 12 of the chiplet pulls down the first acknowledgment signal. The data transmission device 16 synchronizes the first acknowledgment signal in a low level state, and after the synchronization is completed, pulls down the second acknowledgment signal. Thus, the disconnection of the first link is successful.

[0154] Among them, the synchronization of the signal can specifically be cross-clock domain processing, converting the frequency of the signal to a frequency matching that of the receiver. It can be cross-clock domain processing using the same module as described above, or different modules for processing, and the embodiments of the present application do not limit this.

[0155] In the above embodiments, by pulling down the relevant signals, the request process from DTD to the coherent interconnect bus and the acknowledgment process from the coherent interconnect bus to DTD cannot be realized, so as to successfully disconnect the first link.

[0156] In some embodiments, disconnecting the second link between the consistent interconnect bus 12 and the chip interconnect module 14 includes: placing an indication signal in a high level state; the indication signal in a high level state is used to instruct the consistent interconnect bus 12 to place a third request signal in a low level state; in response to the third request signal in a low level state from the consistent interconnect bus 12, synchronizing the third request signal in a low level state; if the synchronization is completed and a link break request is received from the chip interconnect module 14, placing the fourth request signal in a low level state; the fourth request signal in a low level state is used to instruct the chip interconnect module 14 to place a third confirmation signal in a low level state; in response to the third confirmation signal in a low level state from the chip interconnect module 14, synchronizing the third confirmation signal in a low level state; after the synchronization is completed, placing the fourth confirmation signal in a low level state to disconnect the second link.

[0157] After the first link is disconnected successfully, the core-grain interconnect module 14 can transmit a disconnection request through a data signal. For the data transmission device 16, after receiving the data signal transmitted by the core-grain interconnect module 14, it will analyze the data signal, and if the data in the data signal meets the preset disconnection rule, it is determined that a disconnection request has been received. The data in the data signal meets the preset disconnection rule, for example, the value of the preset bit in the data signal is 0.

[0158] The data transmission device 16 pulls up the indication signal and sends the indication signal in a high level state to the consistent interconnect bus 12 of the core particle. If the consistent interconnect bus 12 detects the indication signal in a high level state, the third request signal is pulled down. If the data transmission device 16 receives the third request signal in a low level state transmitted from the consistent interconnect bus 12, the third request signal in a low level state is synchronized. If the synchronization is completed and the link disconnection request transmitted by the core particle interconnect module 14 is received, the fourth request signal is pulled down. Then the core particle interconnect module 14 can pull down the third confirmation signal, so that the data transmission device 16 synchronizes the third confirmation signal. After the synchronization is completed, the fourth confirmation signal is set to a low level state, and at this point, the second link is also successfully disconnected.

[0159] In the above embodiment, by pulling down the relevant signal, the request process from the coherent interconnect bus to the DTD and the confirmation process from the DTD to the coherent interconnect bus cannot be realized, so as to successfully disconnect the second link.

[0160] Specifically, please refer to Figure 8 , Figure 8 The disconnection process of the first link and the second link in an embodiment specifically includes the following steps:

[0161] 1) The DTD pulls down the first request signal CXSB.RXREQ. After the asynchronous bridge receives it, it synchronizes the first request signal CXSB.RXREQ simultaneously, but does not pull down the second confirmation signal CXSB.RXACK;

[0162] 2) After the asynchronous bridge receives the synchronized CXSB.RXREQ_SYNC, it pulls down the second confirmation signal CXSA.TXREQ;

[0163] 3) The CMN pulls down the first confirmation signal CXSA.TXACK in response. After the asynchronous bridge receives it, it synchronizes the first confirmation signal CXSA.TXACK simultaneously;

[0164] 4) After the asynchronous bridge receives the synchronized CXSA.TXACK_SYNC, it pulls down the second confirmation signal CXSB.RXACK. Thus, the following link is successfully disconnected;

[0165] 5) The DTD passes the disconnection request to the LLCTRL through the data signal CXSB.DATA to let the asynchronous bridge initiate a disconnection request;

[0166] 6) The asynchronous bridge raises the indication signal CXSA.RXHINT;

[0167] 7) After the CMN receives the raised indication signal CXSA.RXHINT, it pulls down the third request signal CXSA.RXREQ. After the asynchronous bridge receives it, it synchronizes the third request signal CXSA.RXREQ signal simultaneously;

[0168] 8) After the asynchronous bridge receives the synchronized CXSA.RXREQ_SYNC, it pulls down the fourth request signal CXSB.TXREQ;

[0169] 9) The DTD pulls down the third confirmation signal CXSB.TXACK, and the Bridge synchronizes the third confirmation signal CXSB.TXACK;

[0170] 10) After the asynchronous bridge receives the synchronized CXSB.TXACKSYNC, it pulls down the fourth confirmation signal CXSA.RXACK. Thus, the above link is also successfully disconnected.

[0171] It should be noted that the sending and receiving of relevant signals in the asynchronous bridge are both realized through the corresponding transmitters and receivers.

[0172] In some embodiments, the data transmission method includes the following steps:

[0173] Create a first link between the die interconnect module and the coherent interconnect bus, including: synchronize a first request signal in a high level state in response to the first request signal in a high level state from the die interconnect module; after the synchronization is completed, set a second request signal in a high level state; the second request signal in a high level state is used to instruct the coherent interconnect bus to set a first acknowledgment signal in a high level state; synchronize the first acknowledgment signal in a high level state in response to the first acknowledgment signal in a high level state from the coherent interconnect bus; after the synchronization is completed, set a second acknowledgment signal in a high level state to complete the creation of the first link. The first link is used for the second data transmission.

[0174] Create a second link between the coherent interconnect bus and the die interconnect module, including: synchronize a third request signal in a high level state in response to the third request signal in a high level state from the coherent interconnect bus; if the synchronization is completed and a link establishment request from the die interconnect module is received, set a fourth request signal in a high level state; the fourth request signal in a high level state is used to instruct the die interconnect module to set a third acknowledgment signal in a high level state; synchronize the third acknowledgment signal in a high level state in response to the third acknowledgment signal in a high level state from the die interconnect module; after the synchronization is completed, set a fourth acknowledgment signal in a high level state to complete the creation of the second link. The second link is used for the first data transmission.

[0175] Receive first data from the coherent interconnect bus via a first receiver; the first receiver is adapted to the external interface of the coherent interconnect bus; perform a first conversion on the first data and send the converted first data to the die interconnect module via a first transmitter; the first transmitter is adapted to the external interface of the die interconnect module. Among them, the first conversion includes cross-clock domain processing and at least one of protocol conversion or bit width conversion.

[0176] Receive second data from the die interconnect module via a second receiver; the second receiver is adapted to the external interface of the die interconnect module; perform a second conversion on the second data and send the converted second data to the coherent interconnect bus via a second transmitter; the second transmitter is adapted to the external interface of the coherent interconnect bus. The second conversion includes at least one of protocol conversion or bit width conversion and cross-clock domain processing.

[0177] Disconnect the first link between the die interconnect module and the coherence interconnect bus, including: synchronizing a first request signal in a low level state in response to the first request signal in a low level state from the die interconnect module; after the synchronization is completed, setting a second request signal in a low level state; the second request signal in a low level state is used to instruct the coherence interconnect bus to set a first acknowledgment signal in a low level state; synchronizing the first acknowledgment signal in a low level state in response to the first acknowledgment signal in a low level state from the coherence interconnect bus; after the synchronization is completed, setting a second acknowledgment signal in a low level state to disconnect the first link.

[0178] Disconnect the second link between the coherence interconnect bus and the die interconnect module, including: setting an indication signal in a high level state; the indication signal in a high level state is used to instruct the coherence interconnect bus to set a third request signal in a low level state; synchronizing the third request signal in a low level state in response to the third request signal in a low level state from the coherence interconnect bus; if the synchronization is completed and a link disconnection request from the die interconnect module is received, setting a fourth request signal in a low level state; the fourth request signal in a low level state is used to instruct the die interconnect module to set a third acknowledgment signal in a low level state; synchronizing the third acknowledgment signal in a low level state in response to the third acknowledgment signal in a low level state from the die interconnect module; after the synchronization is completed, setting a fourth acknowledgment signal in a low level state to disconnect the second link.

[0179] In the above embodiments, an asynchronous CXS interface connection is implemented through a new design. And, in order to enable the die interconnect module 14 to recognize the protocol of the coherence interconnect bus (such as the CCIX1.0 protocol of CMN600AE), a CCIX2.0 frame header can be directly added to the CCIX1.0 data during format conversion to avoid the trouble of parsing the CCIX1.0 data; and, the present application also realizes the CXS interface connection with different data bit widths and improves the bandwidth utilization rate. In addition, the present application also designs a link establishment and disconnection process adapted to the coherence interconnect bus and the die interconnect module to ensure the normal operation of the system.

[0180] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0181] In an exemplary embodiment, as Figure 1 shown, a die 10 is provided, which includes a coherent interconnect bus, a data transmission device, a die interconnect module, a processor, and a memory. Among them, the processor is used to provide computing and control capabilities. The memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores a computer program. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor, a data transmission method is implemented.

[0182] Those skilled in the art can understand that Figure 1 the structure shown in

[0183] is only a block diagram of a part of the structure related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0184] In one embodiment, a die is further provided, including a coherent interconnect bus, a data transmission device, a die interconnect module, a memory, and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0185] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0186] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0187] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0188] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A data transmission method, characterized in that: The method is applied to a data transmission device of a chiplet, and a consistent interconnect bus and a chiplet interconnect module are also deployed on the chiplet. The method includes: Receiving first data from the coherent interconnect bus via a first receiver; the first receiver is adapted to an external interface of the coherent interconnect bus; Performing a first conversion on the first data, and sending the converted first data to the chip interconnect module via a first transmitter; the first transmitter is adapted to an external interface of the chip interconnect module; Receiving second data from the chiplet interconnection module via a second receiver; the second receiver is adapted to an external interface of the chiplet interconnection module; Perform a second conversion on the second data, and send the converted second data to the consistent interconnect bus via a second transmitter; the second transmitter is adapted to an external interface of the consistent interconnect bus.

2. The method according to claim 1, characterized in that The first conversion of the first data includes: performing cross-clock domain processing on the first data and then performing format conversion; the second conversion of the second data includes: performing cross-clock domain processing on the second data and then performing format conversion; or The first conversion of the first data includes: performing format conversion on the first data and then performing cross-clock domain processing; the second conversion of the second data includes: performing cross-clock domain processing on the second data and then performing format conversion.

3. The method according to claim 2, characterized in that The format conversion includes at least one of protocol conversion or bit width conversion; the protocol conversion includes at least one of adding a preset frame header or deleting a preset frame header; the bit width conversion includes at least one of data splicing or data splitting.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Creating a first link between the chiplet interconnect module and the coherent interconnect bus; the first link is used for transmitting second data; A second link is created between the coherent interconnect bus and the chiplet interconnect module; the second link is used for transmitting the first data.

5. The method according to claim 4, characterized in that The step of creating a first link between the chiplet interconnect module and the coherent interconnect bus includes: In response to a first request signal in a high level state from the chiplet interconnect module, synchronizing the first request signal in a high level state; After synchronization is completed, the second request signal is placed in a high level state; the second request signal in a high level state is used to instruct the coherent interconnect bus to place the first confirmation signal in a high level state; In response to a first confirmation signal in a high level state from the coherent interconnect bus, synchronizing the first confirmation signal in a high level state; After the synchronization is completed, the second confirmation signal is set to a high level state to complete the creation of the first link.

6. The method according to claim 4, characterized in that The step of creating a second link between the coherent interconnect bus and the chiplet interconnect module includes: In response to a third request signal in a high level state from the coherent interconnect bus, synchronizing the third request signal in a high level state; If the synchronization is completed and a link establishment request is received from the chip interconnect module, the fourth request signal is set to a high level state; the fourth request signal in a high level state is used to instruct the chip interconnect module to set the third confirmation signal to a high level state; In response to a third confirmation signal in a high level state from the chiplet interconnect module, synchronizing the third confirmation signal in a high level state; After the synchronization is completed, the fourth confirmation signal is set to a high level state to complete the creation of the second link.

7. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Disconnecting a first link between the chiplet interconnect module and the coherent interconnect bus; the first link is a link used for second data transmission; Disconnecting a second link between the coherent interconnect bus and the chiplet interconnect module; the second link is a link used for first data transmission.

8. The method according to claim 7, characterized in that The disconnecting the first link between the chiplet interconnect module and the coherent interconnect bus includes: In response to a first request signal in a low level state from a chiplet interconnect module, synchronizing the first request signal in a low level state; After synchronization is completed, the second request signal is placed in a low level state; the second request signal in a low level state is used to instruct the coherent interconnect bus to place the first confirmation signal in a low level state; In response to a first confirmation signal in a low state from the coherent interconnect bus, synchronizing the first confirmation signal in a low state; After synchronization is completed, the second confirmation signal is set to a low level state to disconnect the first link.

9. The method according to claim 7, characterized in that: The disconnecting the second link between the coherent interconnect bus and the chiplet interconnect module includes: placing the indication signal in a high level state; the indication signal in a high level state is used to instruct the coherent interconnect bus to place the third request signal in a low level state; In response to a third request signal in a low state from the coherent interconnect bus, synchronizing the third request signal in a low state; If the synchronization is completed and a disconnection request is received from the chip interconnect module, the fourth request signal is set to a low level state; the fourth request signal in a low level state is used to instruct the chip interconnect module to set the third confirmation signal to a low level state; In response to a third confirmation signal in a low level state from the chiplet interconnect module, synchronizing the third confirmation signal in a low level state; After synchronization is completed, the fourth confirmation signal is set to a low level state to disconnect the second link.

10. A data transmission device, characterized in that: The data transmission device comprises: A first receiver adapted to an external interface of a coherent interconnect bus of the chiplet and configured to receive first data from the coherent interconnect bus; A first conversion module, connected to the first receiver, and configured to perform a first conversion on the first data received by the first receiver; A first transmitter, connected to the first conversion module and adapted to the external interface of the chip-grain interconnection module, for sending the converted first data to the chip-grain interconnection module; A second receiver adapted to the external interface of the chip-grain interconnect module and configured to receive second data from the chip-grain interconnect module; A second conversion module, connected to the second receiver, and configured to perform a second conversion on the second data received by the second receiver; A second transmitter is connected to the second conversion module and adapted to the external interface of the coherent interconnect bus, and is used to send the converted second data to the coherent interconnect bus.

11. The device according to claim 10, characterized in that The first conversion module includes a first format conversion unit and a first synchronization unit, the first format conversion unit is used to perform format conversion on the first data, and the first synchronization unit is used to perform cross-clock domain processing on the first data; The second conversion module includes a second format conversion unit and a second synchronization unit, the second format conversion unit is used to perform format conversion on the second data, and the second synchronization unit is used to perform cross-clock domain processing on the second data.

12. The device according to claim 10, characterized in that The device further includes an extraction module, which is connected to the second receiver and the first transmitter respectively, and is used to identify whether the data signal sent by the core grain interconnect module includes a link establishment request or a link disconnection request.

13. A chiplet, comprising a consistent interconnect bus, a data transmission device, a chiplet interconnect module, a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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