FPGA accelerator card with hard synchronization function

Abstract

The invention provides an FPGA (Field Programmable Gate Array) accelerator card with a hard synchronization function, which comprises an FPGA chip used for processing a computing task issued by a universal processor system, the FPGA chip is provided with a storage module and a power supply module, and external interfaces comprise a PCIE (Peripheral Component Interface Express) interface, a QSFP (Quad Small Form-factor Pluggable) optical interface, an SMA (Shape Memory Alloy) interface and an RS422 interface. And the PCIE interface and the QSFP optical interface are respectively interconnected with the high-speed port of the FPGA module at a high speed. And the storage module, the SMA interface and the RS422 interface are all connected to a general I / O pin of the FPGA. According to the invention, the synchronization signal from the external device can be received, and the PCIE message interrupt is sent to the universal processor system end through the PCIE interface, so that the synchronization time base establishment between the universal processor system and the acceleration card external device is realized. And the message interruption of the PCIE is used as a strong real-time synchronization mode, so that the accurate control on the external equipment can be realized. Meanwhile, the PCIE module and the QSFP optical interface can achieve high-speed data transmission, and the acceleration card supporting strong real-time processing is formed by combining high-density parallel computing of the FPGA.

Description

Technical Field

[0001] The present invention relates to a design of an FPGA acceleration card capable of implementing strong real-time processing, and in particular to an FPGA acceleration card with a hard synchronization function. Background Art

[0002] Traditional signal and information processing systems mainly have three technical routes, which are implemented by processors CPU / GPU / DSP, programmable logic FPGA / CPLD, or application-specific integrated circuits ASIC. The use of processors has the characteristics of convenient programming, good platform versatility, and good scalability; while programmable logic has the characteristics of high flexibility and reconfigurability; and application-specific integrated circuits have the characteristics of more excellent performance and higher energy efficiency.

[0003] Among them, the Field Programmable Gate Array (FPGA) technology has been around for more than 40 years since it was proposed and developed. With the development of information technology, the scale of FPGA's logic resources and processing capabilities have increased exponentially to nearly 10,000 times. Its programmable characteristics allow it to be programmed to meet user-specific needs, and it has the advantages of reconfigurability, low latency, high throughput, low power consumption, and small size. And with the development of software-based radar and communication systems, more and more signal and information processing functions are migrating from FPGA and ASIC to processor systems.

[0004] Although the software of the processor system has the advantage of platform universality, it has the problem of insufficient real-time performance due to serial processing and high-level language programming redundancy, and lack of strict time base. Especially when dealing with peripherals such as sensors and signal detection systems with large throughput and complex signal processing requirements, it is impossible to achieve strong real-time processing. However, the use of PCIE message interrupts can effectively make up for the real-time problem. The essence of the message signaled interrupt is a memory write transaction. This interrupt mechanism uses the memory write request TLP to submit an interrupt request to the CPU without returning to complete the TLP.

[0005] Currently, most accelerator cards are designed only for auxiliary computing functions and do not provide solutions to real-time issues. Summary of the invention

[0006] The purpose of the present invention is to propose an FPGA acceleration card that can effectively solve the synchronization problem of the system and at the same time has the ability to assist the system in processing. To this end, the present invention adopts the following technical solutions:

[0007] A FPGA acceleration card includes an FPGA module, a PCIE interface, a storage module, an SMA interface, an RS422 interface, and a QSFP optical interface. The PCIE interface is connected to the high-speed port of the FPGA. The storage module is electrically connected to the IO port related to the FPGA. The SMA interface and the RSS422 interface are electrically connected to the FPGA. The PCIE interface is connected to the FPGA module, and the transmission protocol is the standard PCIE3.0 protocol; the QSFP optical interface is connected to the high-speed port of the FPGA, and the transmission protocol is 64B / 66B. The power supply solution of this acceleration card meets the voltage requirements of the entire board, provides the working power required by the FPGA module and peripherals, meets the power-on sequence, and the power supply of the power supply circuit is taken from the standard 12V power supply of the PCIE interface.

[0008] The interruption scheme proposed as a solution to the technical problem of the present invention is: the acceleration card has an SMA interface and an RS422 interface, which can receive trigger signals and synchronization signals from external devices, and convert them into PCIE message interrupts in the FPGA module, which are used to establish a synchronous time base between the processor system connected to the PCIE inside the acceleration card and the external device of the acceleration card.

[0009] The data transmission scheme of the present invention is: the acceleration card has a PCIE interface and a QSFP optical interface, which are respectively connected to the high-speed data transmission interfaces of the processor system and the external device, and completes the high-speed transmission protocol conversion through the FPGA module, which can support high-speed data transmission to support strong real-time accelerated computing.

[0010] The present invention utilizes the excellent parallel processing capability of FPGA and the strong real-time characteristics of PCIE message interruption, and proposes an acceleration board solution for auxiliary signal processing for radar or communication systems, which meets the demand for strong real-time performance. The FPGA acceleration card provided by the present invention not only assists the system in high-speed data transmission, but also supports the system synchronization function. It can receive a synchronization signal from an external device or sensor, and then send a PCIE message interrupt to the general processor system through PCIE, so that the general processor system can respond quickly. The present invention uses the PCIE message interruption as a hard synchronization method, which can realize the precise timing control of external devices and sensors. At the same time, the PCIE module and QSFP optical interface carried by the acceleration card of the present invention can realize high-speed output transmission, and the board effectively realizes the strong real-time big data throughput auxiliary calculation function. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0012] Figure 1 This is a schematic diagram of the structure of an FPGA acceleration card with hard synchronization function proposed by the present invention.

[0013] Figure 2 This is a schematic diagram of the FPGA side configuration of the FPGA acceleration card of the present invention.

[0014] Figure 3 This is a schematic diagram of the PCIE interface of the FPGA acceleration card of the present invention.

[0015] Figure 4 This is a schematic diagram of the high-speed interface Bank on the FPGA side corresponding to the PCIE of the FPGA acceleration card of the present invention.

[0016] Figure 5 This is a comparison chart of the CPU response time when the FPGA acceleration card of the present invention uses an MSI message interrupt and when the CPU uses an MSI message interrupt.

[0017] Figure 6 This is a physical diagram of a circuit board for implementing the FPGA acceleration card of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention will be fully described below, but it is not limited to the following embodiments and can be adjusted according to actual conditions.

[0019] The following is a detailed description of the application of the present invention to radar as an example in conjunction with the accompanying drawings.

[0020] like Figure 1 As shown, it is an FPGA acceleration card, which is mainly used for auxiliary signal processing of radar jammer system and provides strong real-time processing capability, including FPGA module 1, PCIE interface 2, storage module 7, SMA interface 5, QSFP optical interface 3, RS422 interface 6 and power supply circuit 4; PCIE interface 2 and QSFP optical interface 3 are connected to the high-speed port of FPGA module 1, and storage module 7, SMA interface 5 and RS422 interface 6 are all connected to the general IO pins of FPGA;

[0021] Among them, the implementation method of FPGA module 1 can use FPGA chip, which is used to process additional computing tasks such as echo simulation from the jammer system; the FPGA chip has an external DDR storage module 7, which is used to store data from the jammer system and wait for FPGA processing; the external interface includes PCIE interface 2, which mainly provides PCIE message interrupt function, which is used to allow the general processor system to send echo commands in real time; the remaining external interfaces such as QSFP optical interface 3, SMA interface 5 and RS422 interface 6 are used to transmit jammer system related data and commands. According to different usage environments, the above-mentioned FPGA accelerator card can select FPGA chips with larger logic resources to meet data processing needs.

[0022] Preferably, the FPGA chip used in this acceleration card is the Kintex series Ultrascale FPGA of XILINX, model XCKU060-FFVA1156, which has up to 720,000 logic units, supports multiple I / O standards and interface protocols, and can effectively complete the signal processing tasks sent by the system. Figure 2 In the figure, it is the configuration bank of the selected FPGA chip. M1, M2, and M3 are the power-on reset mode configuration pins. The design pulls them up by default through the pull-up resistor, and pulls them down externally by the DIP switch to achieve flexible mode selection. The INIT_B and DONE indication signals drive the light-emitting diode to turn on and off by controlling the MOS tube switch, so as to intuitively display the power-on configuration. In fact, the configuration pins are all connected through the pull-up method recommended by the chip manual. For the use of the rest of the Bank, all single-ended signals include RS422, trigger signal, QSFP single-ended control signal, fan control signal, and power enable and POWER GOOD signals. The BANK VCCO power supply is 3.3V, so that the above single-ended signals output high level is 3.3V. P26 is an external 100MHz global clock input pin, which is responsible for the use of FPGA chip logic.

[0023] In this embodiment, the selected FPGA chip configuration method includes JTAG configuration, which is led to the TYPE-C physical interface through a TYPE-C to JTAG protocol conversion chip, and the PC can configure the FPGA chip function through the TYPE-C interface. Among them, the JTAG signal of the conversion chip is connected to the dedicated JTAG pin of the FPGA chip; each USB2.0 differential signal line is connected to a TVS diode to ground to ensure anti-static capability; the conversion chip power supply uses the 3.3V power supply on the board.

[0024] Preferably, the TYPE-C to JTAG chip used is FT232HQ.

[0025] In this embodiment, the selected FLASH chip is a common FLASH chip, which stores the bit files required for the FPGA chip to work and is used to configure the FPGA through the QSPI protocol when the chip is powered on. The chip DQ pin and the CS chip select chip are pulled up to the 3.3V power supply through resistors and connected to the dedicated configuration pins on the FPGA end.

[0026] Preferably, the NOR FLASH chip used is MT25QL01GBBB1EW9-0SIT with a capacity of 1Gbit.

[0027] Figure 1In this embodiment, the storage module 7 selected is a common DDR4 chip, which can store a large amount of data signals transmitted from the optical module and PCIE, and is used for subsequent PFGA signal processing. The specific schematic design consists of four DDR4 chips, each with a capacity of 1GB and a data width of 16 bits, connected to three consecutive banks of the FPGA, and the connection method is completely in accordance with the Xilinx chip manual. At the same time, all DDR4 address control buses are matched through the VTT terminal to ensure the stability and reliability of the address and control signals.

[0028] Figure 1 In the figure, PCIE interface 2 complies with the PCIE3.0 protocol specification. It is connected to the high-speed interface of the FPGA chip that supports PCIE transmission. The PCIE Gen3.0×16 used in this accelerator card indicates that the third-generation PCIE is used, and there are 16 pairs of receiving and transmitting channels. PCIE3.0 is backward compatible with previous versions, and the rate of a single-channel unidirectional bandwidth reaches 1GB / s, and the bidirectional bandwidth of 16 channels reaches 32GB / s. Compared with previous generations, the encoding and decoding method has been changed to 128b / 130b, which greatly improves efficiency. Therefore, the PCIE interface of this accelerator card also meets the needs of large-bandwidth data transmission.

[0029] Figure 3 This is a 16x PCIE interface schematic design, in which the PCIE reset signal is connected to the HR Bank of the FPGA chip through a 1-bit buffer, and the 16-way high-speed serial IO interface is connected to the high-speed interface Bank of the FPGA.

[0030] Figure 4 The schematic diagram shows four consecutive high-speed port banks of the FPGA chip. Each bank has four pairs of high-speed transceiver serial interfaces, a total of 16 pairs, connected to 16x PCIE, and the DC signal is filtered out through AC coupling capacitors in the middle.

[0031] In the above, the MSI message interrupt initiates a request to the CPU through the memory write message transaction packet, and does not need to return the transaction packet. At the same time, because the speed of PCIe3.0 is greatly improved compared with the previous generations of PCIe, the MSI message interrupt greatly shortens the interrupt response time.

[0032] Figure 1In the system, the QSFP optical interface is used to receive other unprocessed data in the system and transmit it to the FPGA chip for auxiliary processing or further processing. QSFP stands for Quad Small Form-factor Pluggable. It has four channels with a total transmission rate of 40Gbps, which can perform high-speed data transmission with the system. The FPGA acceleration card schematic design of the present invention connects two optical modules with a total of 8x high-speed serial lines to two adjacent MGT Banks of the FPGA, and the I2C and control signals of the optical modules are connected to the HR Bank of the FPGA.

[0033] Figure 1 In the power supply circuit, the power supply circuit is responsible for providing the appropriate power supply to the entire board, including controlling the power-on sequence of the power supply required by the FPGA. The core power supply and MGTAVCC are provided by an LTM4620EY dual-channel power supply chip, which converts the 12V power supply into 0.95V and 1.0V, and then an LTM4644IY four-way power supply chip generates 3.6V, two 1.2V, and 1.8V power supplies. The 3.6V is used to generate 2.5V and 3.3V analog power supplies through LDO; one 1.2V is provided to the DDR4 chip power supply and 1.2V VCCO; another 1.2V is provided to the MGTAVTT required by the FPGA high-speed bank; and finally the 1.8V power supply is provided to the FPGA chip auxiliary power supply and 1.8V VCCO.

[0034] The clock scheme of the whole board is that all chip clocks are provided by crystal oscillators: the system clock required by the FPGA chip is designed to obtain a differential clock from the external interface J30J, or a single-ended 100MHz clock from the SMA RF connector; the FPGA's DDR4IP core reference is connected to the FPGA's dedicated clock pin by a crystal oscillator with a frequency of 200MHz and a level standard of LVDS through AC coupling; the clock required by the optical module is also directly provided by the crystal oscillator.

[0035] The external interface of the present invention includes a 9-pin J30J-9ZKWP7-J interface in addition to the QSFP optical interface. In addition to providing an external clock, it also includes an RS422 interface and a single-ended start signal as a control signal; the specific model of the SMA radio frequency interface is SMA-KWHD4. In addition to the single-ended clock, it can also be used as an input port for a trigger signal by selecting a resistor. It can be used to receive synchronization signals from the system. The synchronization is achieved by the FPGA acceleration card receiving the synchronization signal from the system through the SMA and transmitting it to the FPGA. The FPGA then sends a message interrupt to the general processor system through the PCIE controller to ensure that the general processor system accurately sends the control signal.

[0036] Figure 5In the process, the radar sends a synchronization signal to the accelerator card, which then sends it to the general processor system through the PCIE MSI message interrupt. Compared with the method without MSI message interrupt, the CPU response time using MSI message interrupt can reach 1us, while the CPU response time without MSI message interrupt is about 100us.

[0037] Figure 6 The following is a hardware diagram of the FPGA accelerator card. The specific locations of all major modules in the picture have been marked, including FPGA module 1, PCIE interface, DDR storage module 7, SMA interface 5, RS422 interface 6, QSFP optical interface 3, and power supply module 4. Among them, PCIE interface 2 is implemented as a PCIE gold finger, which is compatible with the standard 16x transceiver PCIE slot; QSFP optical interface 3 is implemented by using a QSFP+ optical module, which is matched with a shell component to achieve optical fiber plug-in; RS422 interface 6 is implemented by using a 9PIN J30J connector, and the signal distribution is customized to meet actual needs. The trigger signal uses an SMA interface, and the specific location is as follows: Figure 6 As shown in the figure, the FPGA module is cooled by using a fixed custom fan, and the fan power supply is connected to the 2PIN XHB interface on the board through an external cable.

Claims

1. An FPGA accelerator card with hard synchronization function, characterized in that: It comprises an FPGA module (1), a PCIE interface (2), a storage module (7), an SMA interface (5), a QSFP optical interface (3), an RS422 interface (6) and a power supply circuit (4); the PCIE interface (2) and the QSFP optical interface (3) are connected to the high-speed port of the FPGA module (1), and the DDR storage module (7), the SMA interface (5) and the RS422 interface (6) are all connected to the general IO pins of the FPGA; The interconnection method of the PCIE interface (2) and the FPGA module (1) uses a chip-specific PCIE IP core as a PCIE controller, and the transmission protocol is a standard PCIE3.0 protocol; the interconnection method of the QSFP optical interface (3) and the FPGA module (1) uses a 64B / 66B transmission protocol.

2. The FPGA acceleration card with hard synchronization function according to claim 1, characterized in that: The SMA interface (5) and the RS422 interface (6) can receive trigger signals and synchronization signals from external devices, and convert them into PCIe message interrupts in the FPGA module (1), which are used to establish a synchronous time base between the processor system connected to the PCIe inside the acceleration card and the external device of the acceleration card, and cooperate with the high-density parallel computing of the FPGA module (1) to achieve highly real-time accelerated computing.

3. The FPGA acceleration card with hard synchronization function according to claim 1, characterized in that: The PCIE interface (2) and the QSFP optical interface (3) are respectively connected to the high-speed data transmission interface of the processor system and the external device, and the high-speed transmission protocol conversion is completed through the FPGA module (1), which can support high-speed data transmission and thus support accelerated computing with strong real-time performance.

4. The FPGA acceleration card with hard synchronization function according to claim 1, characterized in that: The power supply circuit (4) provides the working power required by the FPGA module (1) and the peripherals, meets the power-on sequence, and the power supply of the power supply circuit (4) is taken from the standard 12V power supply of the PCIE interface (2).

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