PCSPMA 10-gigabit Ethernet data communication system

Abstract

The invention relates to the technical field of high-speed data transmission control, and discloses a PCSPMA 10-gigabit Ethernet data communication system which comprises a user interface module, a receiving module, a sending module, a descrambling module, a scrambling module, a search synchronous locking control module and a hardcore configuration control module. According to the invention, data scrambling / descrambling (a parallel operation shift register mode) is realized by adopting RTL (Register Transfer Language) design; based on XilinxGigabit Transceiver hardcore development, a Buffer Bypass mode design is selected, the delay is lower and fixed, the deviation between Lanes is small, a Gear Box transmission technology is adopted, a Slip Bit search synchronization algorithm is achieved, clock domain rate matching processing is completed, and low-delay PCSPMA in multi-path 10-gigabit Ethernet communication is achieved. Standard AxiStream bus user interface conversion is realized, and convenience is brought to transplantation and multiplexing; meanwhile, user-defined development of high-speed data transmission based on 64B / 66B coding technology is supported; the method has the advantages of being stable in performance, low in data transmission delay, reliable, capable of supporting user-defined development, high in flexibility and compatibility and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission control, and in particular to a PCSPMA 10 Gigabit Ethernet data communication system. Background Art

[0002] With the rapid development of avionics and communication technologies, the performance and complexity of aircraft are gradually improving, and there are more and more airborne networking devices. The requirements of host manufacturers for data communication rate and response speed between airborne products are increasing.

[0003] Airborne networking equipment is becoming more and more complex, and bandwidth requirements are increasing. Due to the increase in the number of cascade levels, the accumulation of data transmission delays will cause the entire system response speed to decrease, directly affecting the performance of the entire system. This has also become a problem that host manufacturers urgently need to solve.

[0004] At present, the mainstream in the market is the control method with MAC controller + PHY chip as the core to realize Ethernet communication. In this method, the MAC controller needs to configure the PHY chip for data interaction, which is costly and less flexible.

[0005] Xilinx's FPGA integrates the Gigabit Transceiver hard core, supports high-speed serial bus development, and has the characteristics of high performance, low latency, parallel computing, flexible programming, and low development cost, making it an optimal platform for achieving high-speed data transmission. Summary of the invention

[0006] In view of the above-mentioned deficiencies in the prior art, the present invention provides a PCSPMA 10 Gigabit Ethernet data communication system, which can effectively solve the delay problem in 10 Gigabit Ethernet communication; and supports users to customize and develop a high-speed bus with low-latency 64B / 66B encoding technology.

[0007] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0008] A PCSPMA 10 Gigabit Ethernet data communication system, comprising:

[0009] A user interface module, a receiving module, a transmitting module, a descrambling module, a scrambling module, a search synchronization lock control module and a hard core configuration control module;

[0010] The hard core configuration control module is used to receive external optical fiber differential data, perform serial-to-parallel conversion on the differential data and transmit it to the search synchronization lock control module; receive the parallel data scrambled by the scrambling module and the transmission sequence generated by the transmission module, convert the parallel data into serial data and transmit it to the external differential optical fiber interface;

[0011] The search synchronization lock control module is used to synchronize the parallel data converted by the hard core configuration control module and then transmit it to the descrambling module;

[0012] The descrambling module is used to descramble the parallel data synchronized by the search synchronization lock control module and then transmit it to the receiving module;

[0013] The receiving module is used to perform Ethernet control protocol coding analysis and Axi Stream data conversion on the parallel data descrambled by the descrambling module, and transmit the Axi Stream data stream to the user interface module;

[0014] The user interface module is used to receive the Axi Stream data stream and transmit the Axi Stream data stream to the sending module;

[0015] The sending module is used to encode the Axi Stream data stream using the Ethernet control protocol and transmit it to the scrambling module and the hard core configuration control module;

[0016] The scrambling module is used to scramble the encoded data and then transmit it to the hard core configuration control module.

[0017] Preferably, the hard core configuration control module includes a Gt_Common module, a Common_Reset module and a Gt_Channel module;

[0018] The Gt_Common module is used to perform frequency and phase discrimination of the reference clock through the QPLL primitive parameter configuration, and generate the QPLLOUTREFCLK_OUT and QPLLLOCK_OUT clocks required by the PCS layer and the PMA layer in the back-end Gt_Channel module;

[0019] The Common_Reset module is used to perform asynchronous reset and synchronous release;

[0020] The Gt_Channel module is used to instantiate the Gigabit Transceiver hard core, divide the main body into a physical medium adaptation layer and a physical coding sublayer, and build an Ethernet PHY layer controller by configuring the functional interface and logic timing control of the physical coding sublayer in the Gigabit Transceiver hard core.

[0021] Preferably, the configuration information of the Gigabit Transceiver hard core includes:

[0022] The communication line rate is 10Gbps, the encoding method is 64B / 66B controlled by external sequence, the external data bit width is 64bit, the internal data bit width is 32bit, the user-side reference clock is 156.25Mhz, the Buffer Enable mode is disabled, and the TX Buffer Bypass Mode is used.

[0023] Preferably, the search synchronization lock control module specifically uses a search synchronization algorithm to generate a synchronization flag signal and combines the RX Gear Box gearbox to perform clock domain rate matching.

[0024] Preferably, the search synchronization lock control module generates a RXGEARBOXSLIP synchronization sliding window flag to stimulate the RX Gear Box to slide the window of the synchronization head, and moves the window once each high pulse until the synchronization head is searched, completing the clock domain rate matching process.

[0025] Preferably, the descrambling module uses a parallel logic operation mode of a shift register plus sequential logic, and performs descrambling processing according to the scrambling result of deriving parallel 64-bit data output in one clock beat.

[0026] Preferably, the receiving module specifically parses the decoded data between the start bit and the end bit in the Ethernet control protocol coding structure and outputs it to the user's Axi_Stream port, caches the input signal through a group of shift registers, and when the received data synchronization is completed, the synchronization header is 2'b10 and the first byte data bit of the first data received is 8'h78, the sof signal is pulled high to indicate that the frame header is detected; and the Ethernet control protocol coding structure is used to solve and locate the valid data of the bytes contained in the end of the frame, and synchronize to the mask signal of Axi_Stream, when the eof signal is pulled high, it indicates that the end of the frame is detected; at the same time, the lowest byte of the end bit is removed to complete the conversion of the GTX little-endian aligned data into the big-endian aligned data of the user layer.

[0027] Preferably, the sending module specifically receives data through the user layer Axi_Stream interface, converts the data into little-endian mode and temporarily stores it through the internal FIFO IP data; after receiving the user layer data, it starts to frame according to the Ethernet control protocol coding structure until the FIFO is read empty, and outputs the user data, synchronization header and external counting sequence at the same time; and generates a control code for the last data of the data frame through the user layer tail mask signal; uses an internal counter to calculate the data length, generates a stop bit for framing according to the Ethernet control protocol coding structure and the status of the mask of the user tail data, and uses a decimal counter of 32 to generate a sending sequence to control the output data and synchronization header.

[0028] Preferably, the Ethernet control protocol coding structure includes two types: data frame and data control mixed frame;

[0029] The synchronization header of the data frame is 01, and the remaining 64 bits are all data;

[0030] The synchronization header of the data control mixed frame is 10, followed by an 8-bit data control mixed frame type field, indicating the type of this frame, and the remaining 56 bits are data or control codes.

[0031] Preferably, the scrambling module uses a parallel logic operation mode of a shift register plus sequential logic, and performs scrambling processing according to a scrambling code result outputted in one clock beat of the parallel 64-bit data.

[0032] The present invention has the following beneficial effects:

[0033] The present invention adopts RTL design to realize data scrambling / descrambling (shift register mode of parallel operation); based on Xilinx Gigabit Transceiver hard core development, Buffer Bypass mode design is selected, the delay is lower and fixed, the skew between Lanes is small, Gear Box transmission technology is adopted to realize Slip Bit search synchronization algorithm, complete clock domain rate matching processing, and realize low-latency PCSPMA in multi-channel Gigabit Ethernet communication; realize standard Axi_Stream bus user interface conversion, which is convenient for transplantation and multiplexing; at the same time, it supports user-defined development of high-speed data transmission based on 64B / 66B encoding technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the PCSPMA 10 Gigabit Ethernet data communication system principle;

[0035] Figure 2 This is a diagram of the Gigabit Transceiver hard core configuration. ;

[0036] Figure 3 This is the TX Buffer Bypass Mode diagram;

[0037] Figure 4 RX Gear Box transmission block diagram for external generation sequencer;

[0038] Figure 5 RX Gear Box transmission control timing for externally generated sequencers;

[0039] Figure 6 Search for the Slip Bit synchronization algorithm state machine control diagram;

[0040] Figure 7 This is the scrambling principle diagram;

[0041] Figure 8 This is the descrambling principle diagram;

[0042] Fig. 9 It is the coding structure diagram of Ethernet control protocol;

[0043] Fig.10 This is the PCSPMA 10 Gigabit Ethernet RTL schematic view. DETAILED DESCRIPTION

[0044] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0045] The present invention adopts FPGA to develop and implement a low-latency 10 Gigabit Ethernet communication system, adopts RTL design to implement data scrambling / descrambling; based on Xilinx Gigabit Transceiver hard core development, selects Buffer Bypass mode design, adopts Gear Box transmission technology to implement Slip Bit search synchronization algorithm to implement clock domain rate matching processing, and realizes low-latency PCSPMA in multi-channel 10 Gigabit Ethernet communication; designs standard Axi_Stream bus user interface conversion; provides user-defined development of high-speed data transmission based on 64B / 66B encoding technology.

[0046] Reference Figure 1 , a PCSPMA 10 Gigabit Ethernet data communication system provided by an embodiment of the present invention includes:

[0047] A user interface module, a receiving module, a transmitting module, a descrambling module, a scrambling module, a search synchronization lock control module and a hard core configuration control module;

[0048] The hard core configuration control module is used to receive external optical fiber differential data, perform serial-to-parallel conversion on the differential data and transmit it to the search synchronization lock control module; receive the parallel data scrambled by the scrambling module and the transmission sequence generated by the transmission module, convert the parallel data into serial data and transmit it to the external differential optical fiber interface;

[0049] The search synchronization lock control module is used to synchronize the parallel data converted by the hard core configuration control module and then transmit it to the descrambling module;

[0050] The descrambling module is used to descramble the parallel data synchronized by the search synchronization lock control module and then transmit it to the receiving module;

[0051] The receiving module is used to perform Ethernet control protocol coding analysis and Axi Stream data conversion on the parallel data descrambled by the descrambling module, and transmit the Axi Stream data stream to the user interface module;

[0052] The user interface module is used to receive the Axi Stream data stream and transmit the Axi Stream data stream to the sending module;

[0053] The sending module is used to encode the Axi Stream data stream using the Ethernet control protocol and transmit it to the scrambling module and the hard core configuration control module;

[0054] The scrambling module is used to scramble the encoded data and then transmit it to the hard core configuration control module.

[0055] The transmission process of receiving data in this embodiment is as follows:

[0056] The Gt_Module hard core configuration control module receives external optical fiber differential data, converts serial data into parallel data, and synchronizes the data with the Slip Bit search synchronization lock control module. It then descrambles the data through the Descrambler module, and then performs Ethernet control protocol coding analysis and Axi Stream data conversion through the RX receiving module, and finally transmits it to the User_Data user interface module.

[0057] The transmission process of sending data in this embodiment is as follows:

[0058] The User_Data user interface module generates a 64-bit wide Axi Stream data stream, which is transmitted to the TX transmission module for Ethernet control protocol encoding and transmitted to the Scrambler scrambling module. The Scrambler scrambling module scrambles the data, and the scrambled parallel data and the transmission sequence generated by the TX transmission module are transmitted to the Gt_Module hard core configuration control module. Finally, the Gt_Module hard core configuration control module converts the parallel data into serial data and sends it through the external differential optical fiber port.

[0059] In an optional embodiment of the present invention, the hard core configuration control module includes a Gt_Common module, a Common_Reset module and a Gt_Channel module;

[0060] The Gt_Common module is used to perform frequency and phase discrimination of the reference clock through the QPLL primitive parameter configuration, and generate the QPLLOUTREFCLK_OUT and QPLLLOCK_OUT clocks required by the PCS layer and the PMA layer in the back-end Gt_Channel module;

[0061] The Common_Reset module is used to perform asynchronous reset and synchronous release;

[0062] The Gt_Channel module is used to instantiate the Gigabit Transceiver hard core, divide the main body into a physical medium adaptation layer and a physical coding sublayer, and build an Ethernet PHY layer controller by configuring the functional interface and logic timing control of the physical coding sublayer in the Gigabit Transceiver hard core.

[0063] Specifically, the Gt Module hard core configuration control module mainly includes the Gt_Common module, Common_Reset module and Gt_Channel module. It adopts a shared clock architecture design, a custom designed PHY layer, and instantiates the Gt_Common module, Common_Reset module and Gt_Channel module in the Gt Module layer, so that users can flexibly set up multi-channel Ethernet transmission and reception.

[0064] The Gt_Common module mainly completes the QPLL primitive parameter configuration, completes the frequency and phase detection of the 156.25Mhz reference clock, and generates the QPLLOUTREFCLK_OUT and QPLLLOCK_OUT clocks required by the PCS layer and PMA layer in the back-end Gt_Channel module; the Common_Reset module mainly completes the asynchronous reset and synchronous release functions.

[0065] The Gt_Channel module instantiates the Gigabit Transceiver hard core, which is mainly divided into PMA (Physical Media Attachment) and PCS (Physical Coding Sublayer). The function of the PMA layer is to realize the data serial-to-parallel conversion and analog part, which is the physical layer and is mainly implemented by the FPGA hard core; the PCS layer realizes the processing of parallel digital signals and belongs to the logic layer, which is mainly implemented by the FPGA logic. By configuring the rich functional interfaces and logic timing control of the Gigabit Transceiver hard core PCS, an Ethernet PHY layer controller is built, thereby realizing the reception and transmission functions of 10 Gigabit Ethernet serial data.

[0066] The Gt_Channel module mainly configures the Gigabit Transceiver hard core, and configures the low-latency PSCPMA layer data reception and transmission through the timing logic control interface. In the 7Series FPGAs TransceiverWizard, the external data bit width is configured to 64Bits, the Encoding of the TX end is enabled to be external sequence control, and the TXBuffer Bypass Mode mode is selected. The external sequence control is to provide the transmission sequence of the TX Gear Box end transmission to achieve clock rate matching on the TX end. The TX Buffer Bypass Mode is a clock phase alignment processing mode.

[0067] See also Figure 2 Detailed configuration information of the 7Series FPGAs Transceiver Wizard: the communication line rate is 10Gbps, the encoding method is 64B / 66B controlled by the external sequence, the external data width is 64bit, the internal data width is 32bit, the user-side reference clock is 156.25Mhz, the Buffer Enable mode is disabled, and the TX BufferBypass Mode mode is used.

[0068] See also Figure 3 TX Buffer Bypass phase alignment can adjust the phase difference between the PISO parallel clock domain and the TX XCLK domain, transfer data from PCS to PISO, and perform TX delay alignment by continuously adjusting the TX USRCLK to compensate for temperature compensation and voltage changes. Compared with the TX Buffer mode, phase alignment uses fewer register resources, avoids additional data paths caused by longer logic levels, and has lower and fixed delays; at the same time, it shares the same TX USRCLK clock to reduce skew between lanes. TX Buffer Bypass phase alignment adjusts the TX USRCLK to compensate for temperature and voltage timing control steps (according to Figure 3 Interface timing (timing control):

[0069] 1) Set the TXSYNC_OVRD attribute to 1'b1, set TXPHDLYRESET and TXDLYBYPASS of all channels to low, and set TXPHALIGNEN to high;

[0070] 2) Assert the TXDLYSRESET signal high until the TXDLYSRESETDONE signal is asserted;

[0071] 3) Release TXDLYSRESET after the TXDLYSRESETDONE signal is set;

[0072] 4) When TXDLYSRESET is set low, TXPHINIT is set until the TXPHINITDONE signal is detected and TXPHINIT is deasserted;

[0073] 5) Assert TXPHALIGN until a rising edge of TXPHALIGNDONE is detected, then deassert TXPHALIGN;

[0074] 6) Asserting TXDLYEN will cause TXPHALIGNDONE to be set low;

[0075] 7) Keep TXDLYEN until the rising edge of TXPHALIGNDONE is detected;

[0076] 8) TX Delay Alignment continues to adjust the TX USRCLK to compensate for temperature and voltage.

[0077] In an optional embodiment of the present invention, the search synchronization lock control module specifically uses a search synchronization algorithm to generate a synchronization flag signal and combines it with the RX Gear Box gearbox to perform clock domain rate matching.

[0078] The search synchronization lock control module generates the RXGEARBOXSLIP synchronization sliding window flag to stimulate the RX Gear Box to slide the window of the synchronization head, and moves the window once each high pulse until the synchronization head is searched, completing the clock domain rate matching process.

[0079] Specifically, the Slip Bit search synchronization lock control module uses a search synchronization algorithm to generate a synchronization flag signal combined with the RX Gear Box to achieve clock domain rate matching. The Gear Box is a gearbox that realizes the conversion between data bit widths, supporting the conversion of 16-bit, 32-bit, and 64-bit data bit widths. The 64-bit data bit width conversion is used in this embodiment.

[0080] See also Figure 4 The data interaction interface between the RX Gear Box and the Slip Bit module uses 64-bit RX DATA to increase the transmission rate. The Slip Bit module generates the RXGEARBOXSLIP synchronous sliding window flag, and the output interface of the RX Gear Box includes the RX DATAVALID data handshake signal, the RXHEADER synchronous header signal, and the RXHEADER VALID synchronous header handshake signal.

[0081] See also Figure 5The RXGEARBOXSLIP signal is generated according to the RX Gear Box transmission control timing of the external sequencer to stimulate the RX Gear Box to slide the window of the synchronization head. Each high pulse will move the window once until the synchronization head is found and the clock domain rate matching process is completed. The state machine for searching the synchronization head is used to lock the synchronization timing control.

[0082] See also Figure 6 The search synchronization state machine is mainly divided into five states:

[0083] 1) LOCK_INIT: lock initialization state, initialize the lock flag block_lock to false;

[0084] 2) RESET_CNT: Counter reset state, reset header packet counter sh_cnt and invalid header counter sh_invalid_cnt. sh_cnt: In TEST_SH state, there is a header packet counter plus 1, sh_invalid_cnt: In TEST_SH state, there is an invalid header packet counter plus 1;

[0085] 3) TEST_SH: Detect the synchronization header state. When sh_cnt==7'd64 and sh_invalid_cnt==0, jump to COMPLETE_64; when sh_cnt==7'd64 and sh_invalid_cnt>0, jump to RESET_CNT state to reset the counter detection header; when sh_invalid_cnt>=5'd16 or block_lock==0 and invalid_sh==1, jump to SLIP state;

[0086] 4) SLIP: Generates a shift search sync head pulse state, controls the RX Gear Box to move the window for searching the sync head by one beat, generates a SLIP_EN pulse of one clock beat in this state, and generates a counter slip_wait_cnt count of 5'd32 beats and then jumps to the RESET_CNT state;

[0087] 5) COMPLETE_64: When the synchronization head is stably detected, a lock flag is generated. In this state, the block_lock flag is pulled high and the state jumps to the RESET_CNT state for the next detection.

[0088] In an optional embodiment of the present invention, the descrambling module uses a parallel logic operation mode of a shift register plus sequential logic to perform descrambling processing according to the scrambling result of deriving parallel 64-bit data output in one clock beat.

[0089] The scrambling module uses a parallel logic operation mode of a shift register plus sequential logic, and performs scrambling processing according to the scrambling code result outputted by deriving parallel 64-bit data in one clock beat.

[0090] Specifically, the main functions of the Descrambler module and the Scrambler module are to descramble and scramble the data transmitted by the Gt Module, achieve zero-one balance of high-speed serial data, and avoid DC offset and clock recovery difficulties. The digital signal is randomly processed at the bit level to reduce the occurrence of continuous 0 and continuous 1, thereby reducing inter-code interference and jitter, which is beneficial to the clock extraction of the receiving end; at the same time, the baseband signal spectrum is expanded to achieve encryption effect.

[0091] According to the mathematical principle of scrambling (linear feedback shift register LFSR), the circuit model is derived using the polynomial of X(58)+X(19)+1, such as Figure 7 , Figure 8 The structure is used to design the scrambler and descrambler.

[0092] See also Figure 7 , Figure 8 The descrambler module and the scrambler module use the parallel logic operation (AND and OR) mode of shift register plus sequential logic to design the code. The design is based on the scrambling result of deriving the parallel 64-bit data output in one clock beat. This can effectively avoid the burr interference problem of pure combinational logic design, ensure stable communication, and improve bandwidth.

[0093] In an optional embodiment of the present invention, the receiving module specifically parses the decoded data between the start bit and the end bit in the Ethernet control protocol coding structure and outputs it to the user's Axi_Stream port, caches the input signal through a group of shift registers, and when the received data synchronization is completed, the synchronization header is 2'b10 and the first byte data bit of the first data received is 8'h78, the sof signal is pulled high to indicate that the frame header is detected; and the Ethernet control protocol coding structure is used to solve and locate the valid data of the bytes contained in the end of the frame, and synchronize to the mask signal of Axi_Stream, when the eof signal is pulled high, it indicates that the end of the frame is detected; at the same time, the lowest byte of the end bit is removed to complete the conversion of the GTX little-endian aligned data into the big-endian aligned data of the user layer.

[0094] The sending module specifically receives data through the user layer Axi_Stream interface, converts the data into little-endian mode and temporarily stores it through the internal FIFO IP data; after receiving the user layer data, it starts to frame according to the Ethernet control protocol coding structure until the FIFO is read empty, and outputs the user data, synchronization header and external counting sequence at the same time; and generates the control code of the last data of the data frame through the user layer tail mask signal; uses the internal counter to calculate the data length, generates the stop bit of the framing according to the Ethernet control protocol coding structure and the mask status of the user tail data, and uses the decimal counter of 32 to generate the sending sequence to control the output data and synchronization header.

[0095] The Ethernet control protocol coding structure includes two types: data frame and data control mixed frame;

[0096] The synchronization header of the data frame is 01, and the remaining 64 bits are all data;

[0097] The synchronization header of the data control mixed frame is 10, followed by an 8-bit data control mixed frame type field, indicating the type of this frame, and the remaining 56 bits are data or control codes.

[0098] Specifically, see Fig. 9 . The Ethernet control protocol coding structure is divided into two types, one is the data frame and the other is the data control mixed frame. The synchronization header is 01 for the data frame, and the remaining 64 bits are all data; the synchronization header is 10 for the data control mixed frame, followed by an 8-bit data control mixed frame type field, indicating the category of this frame, and the remaining 56 bits are data or control codes. Hari Pattern is the data sent / received by RS (coordination sublayer), where D, Z, T, S, and E are identifiers. D represents data, Z represents idle, T represents end, S represents start, and E represents error. For idle packets, the 7-bit C identifier is filled with 7'd0; for error packets, the 7-bit C identifier is filled with 7'h1e. The invalid area in yellow is filled with 0.

[0099] The main function of the RX receiving module is to convert the data transmitted by the Descrambler module into the Axi Stream data stream format according to the Ethernet control protocol coding structure, and complete the data big-endian and small-endian conversion.

[0100] The RX receiving module parses the decoded data between the start bit and the end bit specified by the Ethernet control protocol coding structure and outputs it to the user's Axi_Stream port. The input signal is cached through a set of shift registers. When the received data synchronization is completed, the synchronization header is 2'b10 and the first byte data bit of the first data received is 8'h78, the sof signal is pulled high to indicate that the frame header is detected. There are 8 situations at the end of the frame. The Ethernet control protocol coding structure is used to calculate and locate the valid data containing several bytes at the end of the frame, and synchronize to the mask signal of Axi_Stream. When the eof signal is pulled high, it indicates that the end of the frame is detected. At the same time, the lowest byte of the end bit is removed to complete the conversion of the GTX little-endian aligned data into the big-endian aligned data of the user layer.

[0101] The main function of the TX sending module is to convert the Axi Stream data stream format output by the User_Data user interface module into the data format input by the Scrambler scrambling module according to the Ethernet control protocol coding structure, and at the same time generate an external sequence for locking synchronization of the sending data end to complete the data big-end conversion.

[0102] The TX transmission module receives data through the user layer Axi_Stream interface, converts the data into little-endian mode and temporarily stores it through the internal FIFO IP data. After receiving the user layer data, it starts to frame according to the Ethernet control protocol coding structure until the FIFO is read empty, and outputs the user data, synchronization header and external count sequence at the same time. The control code of the last data of the data frame is generated through the user layer tail mask signal; the internal counter is used to calculate the data length, and the stop bit of the framing is generated according to the Ethernet control protocol coding structure and the mask status of the user tail data; at the same time, a decimal counter of 32 is used to generate the transmission sequence to control the output data and synchronization header.

[0103] See also Fig.10 According to the embodiment described, the design and development is completed to generate the RTL top-level view. The external interface is a 2-way optical fiber differential pair, and the user can expand the Ethernet protocol in the User_Data user interface module.

[0104] The present invention realizes low-latency 10 Gigabit Ethernet PCSPMA on an FPGA platform, and is also suitable for communication application scenarios of user-defined 64B / 66B encoded high-speed data formats.

[0105] The present invention realizes PCSPMA 10 Gigabit Ethernet data communication, has stable performance, low and reliable data transmission delay, and supports users to customize and develop a high-speed bus with low-delay 64B / 66B encoding technology, with high flexibility and compatibility.

[0106] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0107] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A PCSPMA 10 Gigabit Ethernet data communication system, characterized in that: include: A user interface module, a receiving module, a transmitting module, a descrambling module, a scrambling module, a search synchronization lock control module and a hard core configuration control module; The hard core configuration control module is used to receive external optical fiber differential data, perform serial-to-parallel conversion on the differential data, and transmit it to the search synchronization lock control module; Receive the parallel data scrambled by the scrambling module and the sending sequence generated by the sending module, convert the parallel data into serial data and transmit it to the external differential optical fiber interface; The search synchronization lock control module is used to synchronize the parallel data converted by the hard core configuration control module and then transmit it to the descrambling module; The descrambling module is used to descramble the parallel data synchronized by the search synchronization lock control module and then transmit it to the receiving module; The receiving module is used to perform Ethernet control protocol coding analysis and AxiStream data conversion on the parallel data descrambled by the descrambling module, and transmit the Axi Stream data stream to the user interface module; The user interface module is used to receive the Axi Stream data stream and transmit the Axi Stream data stream to the sending module; The sending module is used to encode the Axi Stream data stream using the Ethernet control protocol and transmit it to the scrambling module and the hard core configuration control module; The scrambling module is used to scramble the encoded data and then transmit it to the hard core configuration control module.

2. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The hard core configuration control module includes a Gt_Common module, a Common_Reset module and a Gt_Channel module; The Gt_Common module is used to perform frequency and phase discrimination of the reference clock through the QPLL primitive parameter configuration, and generate the QPLLOUTREFCLK_OUT and QPLLLOCK_OUT clocks required by the PCS layer and the PMA layer in the back-end Gt_Channel module; The Common_Reset module is used to perform asynchronous reset and synchronous release; The Gt_Channel module is used to instantiate the Gigabit Transceiver hard core, divide the main body into a physical medium adaptation layer and a physical coding sublayer, and build an Ethernet PHY layer controller by configuring the functional interface and logic timing control of the physical coding sublayer in the Gigabit Transceiver hard core.

3. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 2, characterized in that: The configuration information of the Gigabit Transceiver hard core includes: The communication line rate is 10Gbps, the encoding method is 64B / 66B controlled by external sequence, the external data bit width is 64bit, the internal data bit width is 32bit, the user-side reference clock is 156.25Mhz, the Buffer Enable mode is disabled, and the TXBuffer Bypass Mode mode is used.

4. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The search synchronization lock control module specifically uses a search synchronization algorithm to generate a synchronization flag signal and combines the RX Gear Box gearbox to perform clock domain rate matching.

5. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 4, characterized in that: The search synchronization lock control module generates the RXGEARBOXSLIP synchronization sliding window flag to stimulate the RX Gear Box to slide the window of the synchronization head, and moves the window once each high pulse until the synchronization head is searched, completing the clock domain rate matching process.

6. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The descrambling module uses a parallel logic operation mode of a shift register plus sequential logic, and performs descrambling processing according to the scrambling result of deriving parallel 64-bit data output in one clock beat.

7. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The receiving module specifically parses the decoded data between the start bit and the end bit in the Ethernet control protocol coding structure and outputs it to the user's Axi_Stream port, caches the input signal through a group of shift registers, and when the received data synchronization is completed, the synchronization header is 2'b10 and the first byte data bit of the first data received is 8'h78, the sof signal is pulled high to indicate that the frame header is detected; and the Ethernet control protocol coding structure is used to solve and locate the valid data containing bytes at the end of the frame, and synchronize to the mask signal of Axi_Stream, when the eof signal is pulled high, it indicates that the end of the frame is detected; at the same time, the lowest byte of the end bit is removed to complete the conversion of GTX little-endian aligned data into big-endian aligned data of the user layer.

8. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The sending module specifically receives data through the user layer Axi_Stream interface, converts the data into little-endian mode and temporarily stores it through the internal FIFO IP data; after receiving the user layer data, it starts to frame according to the Ethernet control protocol coding structure until the FIFO is read empty, and outputs the user data, synchronization header and external counting sequence at the same time; and generates the control code of the last data of the data frame through the user layer tail mask signal; uses the internal counter to calculate the data length, generates the stop bit of the framing according to the Ethernet control protocol coding structure and the mask status of the user tail data, and uses the decimal counter of 32 to generate the sending sequence to control the output data and synchronization header.

9. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 7 or 8, characterized in that: The Ethernet control protocol coding structure includes two types: data frame and data control mixed frame; The synchronization header of the data frame is 01, and the remaining 64 bits are all data; The synchronization header of the data control mixed frame is 10, followed by an 8-bit data control mixed frame type field, indicating the type of this frame, and the remaining 56 bits are data or control codes.

10. A PCSPMA 10 Gigabit Ethernet data communication system according to claim 1, characterized in that: The scrambling module uses a parallel logic operation mode of a shift register plus sequential logic, and performs scrambling processing according to the scrambling code result outputted by deriving parallel 64-bit data in one clock beat.

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