Butterfly computing unit, butterfly computing unit array, reconfigurable array and chip

Abstract

The embodiment of the invention provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip. The butterfly computing unit comprises a first-in first-out cache unit, a butterfly computing module, a multiplier module, a twiddle factor storage module, a first external interface and a second external interface. The first external interface inputs radix-2 or radix-3 FFT data. And the first-in first-out cache unit caches the input data or the data output by the butterfly computing module or the data output by the multiplier module. And the butterfly calculation module receives the data output by the first-in first-out cache unit, and performs butterfly calculation to obtain butterfly calculation result data. And the multiplier module obtains the twiddle factor from the twiddle factor storage module and performs multiplication calculation on the data output by the first-in first-out cache unit or the data output by the butterfly calculation module according to the twiddle factor to obtain multiplication calculation result data. And the second external interface sends out multiplication calculation result data. According to the invention, the structure of the butterfly computing unit is simplified, and the hardware resource consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip. Background Art

[0002] In modern computing, butterfly computing units are widely used in signal processing tasks such as Fast Fourier Transform (FFT). The efficient computing capability of the butterfly structure enables it to quickly process complex mathematical operations.

[0003] In the related art, a butterfly operator is provided. However, the butterfly operator has a complex structure and consumes a large amount of hardware resources when executing a butterfly operation. Summary of the invention

[0004] The embodiments of the present application provide a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip to achieve the technical effect of reducing the structural complexity of the butterfly operator and reducing the hardware resources consumed by the butterfly operator to perform a butterfly operation.

[0005] In a first aspect, an embodiment of the present application provides a butterfly computing unit, comprising: a first-in-first-out cache unit, a butterfly computing module, a multiplier module, a twiddle factor storage module, a first external interface, and a second external interface;

[0006] The first-in-first-out cache unit is connected to the butterfly calculation module, the multiplier module, the first external interface and the second external interface respectively, the butterfly calculation module is connected to the multiplier module, and the multiplier module is connected to the rotation factor storage module and the second external interface;

[0007] A first external interface is used to input data in a radix-2 or radix-3 frequency domain extraction fast Fourier transform mode, wherein the data in the radix-2 and radix-3 frequency domain extraction fast Fourier transform mode both include multiple groups of data;

[0008] The first-in-first-out cache unit is used to cache at least one set of data or the butterfly calculation result data output by the butterfly calculation module or the multiplication calculation result data output by the multiplier module;

[0009] The butterfly calculation module is used to receive the data output by the first-in first-out cache unit, and perform butterfly calculation on the data output by the first-in first-out cache unit to obtain butterfly calculation result data;

[0010] The multiplier module is used to obtain the rotation factor from the rotation factor storage module, and perform multiplication calculation on the butterfly calculation result data output by the first-in first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain the multiplication calculation result data;

[0011] The second external interface is used to send out the multiplication result data.

[0012] In a possible implementation, the first-in-first-out cache unit includes: a first first-in-first-out cache module, a second first-in-first-out cache module, and a third first-in-first-out cache module;

[0013] The first FIFO cache module input end is respectively connected to the butterfly computing module output end and the first external interface input end, and the first FIFO cache module output end is connected to the butterfly computing module input end;

[0014] The second FIFO buffer module input end is respectively connected to the butterfly calculation module output end and the first external interface input end, and the second FIFO buffer module output end is respectively connected to the butterfly calculation module input end and the multiplier module input end;

[0015] The input end of the third FIFO buffer module is connected to the output end of the multiplier module, and the output end of the third FIFO buffer module is respectively connected to the input end of the butterfly calculation module and the input end of the second external interface.

[0016] In a possible implementation, the butterfly computing module includes: a first input interface, a first output interface, a second input interface, and a second output interface;

[0017] The first input interface is respectively connected to the first FIFO buffer module output end, the second FIFO buffer module output end and the first external interface input end, and the first output interface is respectively connected to the first FIFO buffer module input end and the second external interface input end;

[0018] The second input interface is connected to the output end of the first FIFO buffer module, the output end of the second FIFO buffer module and the input end of the first external interface respectively, and the second output interface is connected to the input end of the second FIFO buffer module.

[0019] In a possible implementation manner, the data outputted from the first external interface input terminal at least includes a first group of data and a second group of data, wherein the first group of data and the second group of data are data in a base-2 frequency domain decimation fast Fourier transform mode;

[0020] The first external interface is specifically used to: send the first set of data to the first first-in first-out cache module, and send the second set of data to the second input interface of the butterfly calculation module;

[0021] The butterfly calculation module is specifically used to: receive the first group of data sent by the first first-in-first-out cache module, and perform a first butterfly calculation according to the first group of data and the second group of data to obtain first butterfly calculation result data and second butterfly calculation result data, and send the first butterfly calculation result data to the second external interface through the first output interface, and send the second butterfly calculation result data to the second first-in-first-out cache module through the second output interface;

[0022] The multiplier module is specifically used to: receive the second butterfly calculation result data sent by the second first-in-first-out cache module, read the first rotation factor stored in the rotation factor storage module, and perform complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain first multiplication calculation result data, and send the first multiplication calculation result data to the third first-in-first-out cache module, so that the first multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

[0023] In a possible implementation manner, the data outputted from the first external interface input terminal at least includes a third group of data, a fourth group of data and a fifth group of data, wherein the third group of data, the fourth group of data and the fifth group of data are data in a base-three frequency domain decimation fast Fourier transform mode;

[0024] The first external interface is specifically used to: send the third group of data to the second first-in first-out cache module, send the fourth group of data to the first first-in first-out cache module, and send the fifth group of data to the second input interface of the butterfly calculation module;

[0025] The butterfly calculation module is specifically used to: receive the fourth group of data sent by the first first-in-first-out cache module, and perform a second butterfly calculation according to the fourth group of data and the fifth group of data to obtain third butterfly calculation result data and fourth butterfly calculation result data, and send the third butterfly calculation result data to the first first-in-first-out cache module through the first output interface, and send the fourth butterfly calculation result data to the second first-in-first-out cache module through the second output interface;

[0026] The multiplier module is specifically used to: receive the fourth butterfly calculation result data sent by the second first-in-first-out cache module, read the second rotation factor stored in the rotation factor storage module, perform constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain second multiplication calculation result data, and send the second multiplication calculation result data to the third first-in-first-out cache module.

[0027] In a possible implementation manner, the butterfly computing module is further used to:

[0028] receiving the third butterfly calculation result data sent by the first first-in-first-out buffer module, and receiving the third set of data sent by the second first-in-first-out buffer module;

[0029] Perform a third butterfly calculation according to the third butterfly calculation result data and the third group of data to obtain fifth butterfly calculation result data and sixth butterfly calculation result data;

[0030] The fifth butterfly calculation result data is sent to the second external interface through the first output interface, and the sixth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

[0031] In a possible implementation manner, the butterfly computing module is further used to:

[0032] receiving the sixth butterfly calculation result data sent by the second FIFO buffer module, and receiving the second multiplication calculation result data sent by the third FIFO buffer module;

[0033] Performing a fourth butterfly calculation according to the sixth butterfly calculation result data and the second multiplication calculation result data to obtain seventh butterfly calculation result data and eighth butterfly calculation result data;

[0034] The seventh butterfly calculation result data is sent to the multiplier module through the first output interface, and the eighth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

[0035] In a possible implementation manner, the multiplier module is further configured to:

[0036] Receiving the seventh butterfly calculation result data sent by the butterfly calculation module;

[0037] Read the third rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor to obtain third multiplication calculation result data, and send the third multiplication calculation result data to the third first-in-first-out cache module, so that the third multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

[0038] In a possible implementation manner, the multiplier module is further configured to:

[0039] receiving the eighth butterfly calculation result data sent by the second first-in-first-out cache module;

[0040] Read the fourth rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out cache module, so that the fourth multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

[0041] In a second aspect, an embodiment of the present application provides a butterfly computing unit array, comprising a plurality of butterfly computing units as described in the first aspect and / or various possible implementations of the first aspect, wherein the plurality of butterfly computing units are connected in series.

[0042] In a third aspect, an embodiment of the present application provides a hybrid-radix reconfigurable array, comprising a butterfly computing unit array as described in the second aspect.

[0043] In a possible implementation, the invention further includes: a memory, an input controller, an output controller and a timing controller;

[0044] The memory is connected to the input controller input terminal, the output controller input terminal and the timing controller input terminal respectively, and the input controller output terminal, the output controller input terminal and the timing controller output terminal are connected to the butterfly computing unit array respectively;

[0045] The memory is used to store configuration information, the configuration information includes data to be operated and an operation mode of the data to be operated, the operation mode includes a base-2 frequency domain extraction fast Fourier transform mode or a base-3 frequency domain extraction fast Fourier transform mode;

[0046] The timing controller is used to determine the timing logic of each butterfly computing unit in the butterfly computing unit array according to the configuration information;

[0047] The input controller is used to group the data to be operated according to the operation mode to obtain multiple groups of data;

[0048] The output controller is used to receive output result data of the butterfly computing unit array on the data to be calculated.

[0049] In a possible implementation manner, the input controller output terminal, the output controller input terminal, and the timing controller output terminal are respectively connected to a plurality of the butterfly computing units in the butterfly computing unit array.

[0050] In a fourth aspect, an embodiment of the present application provides a chip, comprising a hybrid-based reconfigurable array as described in the third aspect and / or various possible implementations of the third aspect.

[0051] The embodiment of the present application provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip, wherein the butterfly computing unit includes: a first-in-first-out cache unit, a butterfly computing module, a multiplier module, a rotation factor storage module, a first external interface and a second external interface. The connection relationship of the above components is: the first-in-first-out cache unit is connected to the butterfly computing module, the multiplier module, the first external interface and the second external interface respectively, the butterfly computing module is connected to the multiplier module, and the multiplier module is connected to the rotation factor storage module and the second external interface. Among them, the first external interface is used to input data of a base-two or base-three frequency domain extraction fast Fourier transform mode, and the data of the base-two and base-three frequency domain extraction fast Fourier transform modes both include multiple groups of data. The first-in-first-out cache unit is used to cache at least one group of data or the butterfly calculation result data output by the butterfly computing module or the multiplication calculation result data output by the multiplier module. The butterfly computing module is used to receive the data output by the first-in-first-out cache unit, and perform butterfly calculation on the data output by the first-in-first-out cache unit to obtain the butterfly calculation result data. The multiplier module is used to obtain the rotation factor from the rotation factor storage module, and perform multiplication calculation on the butterfly calculation result data output by the first-in first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain the multiplication calculation result data. The second external interface is used to send the multiplication calculation result data. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0053] Figure 1 A schematic diagram of the structure of a butterfly operator in a related technology provided by this application;

[0054] Figure 2A schematic diagram of the structure of a butterfly computing unit provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of the structure of another butterfly computing unit provided in an embodiment of the present application;

[0056] Figure 4 A schematic diagram of the structure of a butterfly computing unit for performing a radix-2 butterfly operation on data in a radix-2 frequency domain decimation fast Fourier transform mode provided in an embodiment of the present application;

[0057] Figure 5A A schematic diagram of the structure of a butterfly computing unit for performing a first set of butterfly operations on data in a base-three frequency domain decimation fast Fourier transform mode provided in an embodiment of the present application;

[0058] Figure 5B A schematic diagram of the structure of a butterfly computing unit for performing a second set of butterfly operations on data in a base-three frequency domain decimation fast Fourier transform mode provided in an embodiment of the present application;

[0059] Figure 5C A schematic diagram of the structure of a butterfly computing unit for performing a third set of butterfly operations on data in a base-three frequency domain decimation fast Fourier transform mode provided in an embodiment of the present application;

[0060] Fig. 6A A schematic diagram of a radix-three butterfly operation structure in a related technology provided by this application;

[0061] Figure 6B A schematic diagram of a radix-three butterfly operation structure provided in an embodiment of the present application;

[0062] Figure 7 A schematic diagram of the structure of a butterfly computing unit array provided in an embodiment of the present application;

[0063] Figure 8 A schematic diagram of the structure of a mixed-radix FFT processor in another related technology provided by the present application;

[0064] Fig. 9 A schematic diagram of the structure of a hybrid-based reconfigurable array provided in an embodiment of the present application;

[0065] Fig.10 A schematic diagram of calculation results provided in an embodiment of the present application;

[0066] Fig.11 A schematic diagram of another calculation result provided in an embodiment of the present application.

[0067] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0068] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0069] In the description of the embodiments of the present application, terms such as "inside" and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings. This is merely for the convenience of description and does not indicate or imply that the device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present application.

[0070] In the description of the embodiments of the present application, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, components, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment.

[0071] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0072] In the related art, there is a multi-channel mixed-radix FFT reconfigurable butterfly operator, such as Figure 1 As shown, Figure 1A schematic diagram of the structure of a butterfly operator in a related technology provided in the present application, wherein the butterfly operator includes a control unit 11, a first selection switch unit 12 and a computing unit 13, wherein the control unit 11 is connected to the first selection switch unit 12 and the computing unit 13 respectively, and the first selection switch unit 12 is connected to the computing unit 13.

[0073] The operation unit 13 includes two radix-2 butterfly operators 131 , a first complex adder 132 and a second complex adder 133 . Each radix-2 butterfly operator 131 includes a first complex multiplier 1311 , a third complex adder 1312 and a complex subtractor 1313 .

[0074] The control unit 11 is used to generate a calculation instruction according to the received data to be calculated, wherein the data to be calculated includes a digital signal to be processed, a rotation factor and a preset rotation factor coefficient.

[0075] The first selection switch unit 12 is used for selecting a corresponding conduction mode according to the operation instruction.

[0076] The operation unit 13 is used to perform butterfly operation on the data to be operated according to the conduction mode. Specifically, the radix-2 butterfly operator 131 is used to perform radix-2 butterfly operation according to the data to be operated and the conduction mode corresponding to the first selection switch unit 12. The two radix-2 butterfly operators 131 are also used to form a radix-3 butterfly operator 14 with the first complex adder 132 and the second complex adder 133 according to the conduction mode corresponding to the first selection switch unit 12, and are used to perform radix-3 butterfly operation on the data to be operated.

[0077] Optionally, the radix-3 butterfly operator 14 includes a second complex multiplier, a third complex multiplier, a complex adder group, a first complex adder, and a second complex adder. The second complex multiplier is a first complex multiplier 1311 in a radix-2 butterfly operator, the third complex multiplier is a first complex multiplier 1311 in another radix-2 butterfly operator, and the complex adder group includes a third complex adder 1312 and a complex subtractor 1313 of two radix-2 butterfly operators.

[0078] However, in the structure of the above-mentioned reconfigurable butterfly operator, the structure of the radix-3 butterfly operator requires, in addition to the first complex adder 132 and the second complex adder 133 required by itself, the first complex multiplier 1311, the third complex adder 1312 and the complex subtractor 1313 of the two radix-2 butterfly operators 131, which results in the overall structure of the reconfigurable butterfly operator being complicated and the hardware resources consumed by the reconfigurable butterfly operator to perform a radix-2 butterfly operation or a radix-3 butterfly operation are relatively large.

[0079] Therefore, in view of the above technical problems in the prior art, the inventors found in the process of research that the reason why the reconfigurable butterfly operator in the above related technology is complicated is that the radix-2 butterfly operator and the radix-3 butterfly operator have their own corresponding structures. Therefore, the inventors found that if the same structure can be used as a radix-2 butterfly operator to perform radix-2 butterfly operations and as a radix-3 butterfly operator to perform radix-3 butterfly operations, the complexity of the overall structure of the reconfigurable butterfly operator can be greatly simplified, thereby reducing the hardware resource consumption of performing a butterfly operation. Based on this, the inventors have improved the reconfigurable butterfly operator, that is, the butterfly computing unit in the present application. Specifically, the butterfly computing unit includes: a first-in-first-out cache unit, a butterfly computing module, a multiplier module, a rotation factor storage module, a first external interface and a second external interface. The connection relationship of the above components is: the first-in-first-out cache unit is connected to the butterfly computing module, the multiplier module, the first external interface and the second external interface respectively, the butterfly computing module is connected to the multiplier module, and the multiplier module is connected to the rotation factor storage module and the second external interface. Among them, the first external interface is used to input data of the radix-2 or radix-3 frequency domain extraction fast Fourier transform mode, and the data of the radix-2 and radix-3 frequency domain extraction fast Fourier transform modes both include multiple groups of data. The first-in-first-out cache unit is used to cache at least one group of data or the butterfly calculation result data output by the butterfly calculation module or the multiplication calculation result data output by the multiplier module. The butterfly calculation module is used to receive the data output by the first-in-first-out cache unit, and perform butterfly calculation on the data output by the first-in-first-out cache unit to obtain the butterfly calculation result data. The multiplier module is used to obtain the rotation factor from the rotation factor storage module, and perform multiplication calculation on the butterfly calculation result data output by the first-in-first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain the multiplication calculation result data. The second external interface is used to send out the multiplication calculation result data. Therefore, the present application proposes a butterfly calculation unit, a butterfly calculation unit array, a reconfigurable array and a chip.

[0080] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0081] See also Figure 2 , Figure 2 A structural schematic diagram of a butterfly computing unit provided in an embodiment of the present application, the butterfly computing unit (PE) includes: a first-in-first-out cache unit 21, a butterfly computing module 22, a multiplier module 23, a rotation factor storage module 24, a first external interface 25 and a second external interface 26.

[0082] The connection relationship can be:

[0083] The FIFO cache unit 21 is connected to the butterfly calculation module 22 , the multiplier module 23 , the first external interface 25 and the second external interface 26 respectively. The butterfly calculation module 22 is connected to the multiplier module 23 . The multiplier module 23 is connected to the rotation factor storage module 24 and the second external interface 26 .

[0084] The functions of each structure can be:

[0085] The first external interface 25 is used to input data in a radix-2 or radix-3 frequency domain extraction fast Fourier transform mode. The data in the radix-2 and radix-3 frequency domain extraction fast Fourier transform mode both include multiple groups of data.

[0086] Optionally, in this embodiment, the first external interface 25 may be a data output port of a previous butterfly computing unit, and data output by the previous butterfly computing unit is input to the butterfly computing unit currently participating in the calculation through the first external interface 25 .

[0087] Optionally, the data output by the previous butterfly computing unit can be data in a radix-2 frequency domain extraction fast Fourier transform mode, i.e., radix-2 DIF-FFT, or data in a radix-3 frequency domain extraction fast Fourier transform mode, i.e., radix-3 DIF-FFT. The data in either radix-2 or radix-3 frequency domain extraction fast Fourier transform mode can include multiple groups of data.

[0088] The FIFO buffer unit 21 is used to buffer at least one set of data or the butterfly calculation result data output by the butterfly calculation module 22 or the multiplication calculation result data output by the multiplier module 23 .

[0089] Optionally, in this embodiment, the FIFO cache unit 21 may include three FIFO cache modules, because the data source received by each FIFO cache module may be at least one set of data input through the first external interface 25, or may be the butterfly calculation result data output by the butterfly calculation module 22, or may be the multiplication calculation result data output by the multiplier module 23. Therefore, the FIFO cache unit 21 may cache the above different data.

[0090] The butterfly calculation module 22 is used for receiving the data output by the FIFO buffer unit 21 and performing butterfly calculation on the data output by the FIFO buffer unit 21 to obtain butterfly calculation result data.

[0091] In the FFT algorithm, the butterfly calculation module 22 is an important component, which can decompose the calculation process of Fourier transform, thereby reducing the amount of calculation.

[0092] Optionally, the butterfly calculation module 22 may include two adders and two subtractors, wherein the adder is used to perform complex addition calculations on the data output by the first-in-first-out cache unit 21, and the subtractor is used to perform complex subtraction calculations on the data output by the first-in-first-out cache unit 21, and the butterfly calculation of the data input into the butterfly calculation module 22 is completed by performing addition and subtraction calculations, thereby obtaining the butterfly calculation result data after the butterfly calculation.

[0093] Optionally, the butterfly computing module 22 may also be connected to the first external interface 25 .

[0094] Optionally, the butterfly calculation module 22 may also be configured to receive group data sent by the first external interface 25 and perform butterfly calculation on the group data.

[0095] The multiplier module 23 is used to obtain the rotation factor from the rotation factor storage module 24, and perform multiplication calculation on the butterfly calculation result data output by the FIFO cache unit 21 or the butterfly calculation result data output by the butterfly calculation module 22 according to the rotation factor to obtain the multiplication calculation result data.

[0096] Optionally, the multiplier module 23 may include four multipliers, an adder and a subtractor. The four multipliers obtain the rotation factors from the rotation factor storage module 24, and multiply the data input to the multiplier module 23 according to the rotation factors, and then perform addition or subtraction respectively to finally obtain the multiplication result data.

[0097] In this embodiment, the twiddle factor storage module 24 stores a plurality of twiddle factors, and this embodiment does not limit the number of the stored twiddle factors.

[0098] The second external interface 26 is used to send out the multiplication result data.

[0099] Optionally, the multiplication result data is sent to the next butterfly computing unit through the second external interface 26 .

[0100] In the above embodiment of the present application, the butterfly calculation unit includes: a first-in-first-out cache unit 21, a butterfly calculation module 22, a multiplier module 23, a rotation factor storage module 24, a first external interface 25 and a second external interface 26. The connection relationship of the above components is: the first-in-first-out cache unit 21 is connected to the butterfly calculation module 22, the multiplier module 23, the first external interface 25 and the second external interface 26 respectively, the butterfly calculation module 22 is connected to the multiplier module 23, and the multiplier module 23 is connected to the rotation factor storage module 24 and the second external interface 26. Among them, the first external interface 25 is used to input data of a base-two or base-three frequency domain extraction fast Fourier transform mode, and the data of the base-two and base-three frequency domain extraction fast Fourier transform modes both include multiple groups of data. The first-in-first-out cache unit 21 is used to cache at least one group of data or the butterfly calculation result data output by the butterfly calculation module 22 or the multiplication calculation result data output by the multiplier module 23. The butterfly calculation module 22 is used to receive the data output by the first-in-first-out cache unit 21, and perform butterfly calculation on the data output by the first-in-first-out cache unit 21 to obtain butterfly calculation result data. The multiplier module 23 is used to obtain the rotation factor from the rotation factor storage module 24, and perform multiplication calculation on the butterfly calculation result data output by the first-in-first-out cache unit 21 or the butterfly calculation result data output by the butterfly calculation module 22 according to the rotation factor to obtain the multiplication calculation result data. The second external interface 26 is used to send out the multiplication calculation result data. The butterfly calculation unit in this embodiment can perform both radix-2 butterfly calculation and radix-3 butterfly calculation through the same structure (first-in-first-out cache unit 21, butterfly calculation module 22, multiplier module 23, rotation factor storage module 24, first external interface 25 and second external interface 26), which improves the reuse rate of each component, simplifies the structure of the butterfly calculation unit, and thus reduces the consumption of hardware resources for executing a radix-2 or radix-3 butterfly calculation.

[0101] Further, based on the above embodiments, the structure of the butterfly computing unit in the present application is described in detail through the following embodiments. Figure 3 , Figure 3 A schematic diagram of the structure of another butterfly computing unit provided in an embodiment of the present application.

[0102] Optionally, in this embodiment, the FIFO buffer unit 21 (FIFO) may include a first FIFO buffer module (FIFO_A) 211 , a second FIFO buffer module (FIFO_B) 212 and a third FIFO buffer module (FIFO_C) 213 .

[0103] The connection relationship between the first FIFO cache module 211, the second FIFO cache module 212 and the third FIFO cache module 213 and the butterfly calculation module 22, the multiplier module 23, the first external interface 25 and the second external interface 26 in the butterfly calculation unit is as follows: Figure 3 As shown:

[0104] The input end of the first FIFO buffer module 211 is respectively connected to the output end of the butterfly calculation module 22 and the input end of the first external interface 25 , and the output end of the first FIFO buffer module 211 is connected to the input end of the butterfly calculation module 22 .

[0105] Optionally, the first FIFO buffer module 211 may receive and buffer input data from the first external interface 25 , and may also receive and buffer butterfly calculation result data output by the butterfly calculation module 22 .

[0106] The input end of the second FIFO buffer module 212 is respectively connected to the output end of the butterfly calculation module 22 and the input end of the first external interface 25 , and the output end of the second FIFO buffer module 212 is respectively connected to the input end of the butterfly calculation module 22 and the input end of the multiplier module 23 .

[0107] Optionally, the second FIFO buffer module 212 may receive and buffer input data from the first external interface 25 , and may also receive and buffer butterfly calculation result data output by the butterfly calculation module 22 .

[0108] The input end of the third FIFO buffer module 213 is connected to the output end of the multiplier module 23 , and the output end of the third FIFO buffer module 213 is connected to the input end of the butterfly calculation module 22 and the input end of the second external interface 26 respectively.

[0109] Optionally, the third FIFO buffer module 213 may receive and buffer the multiplication result data output by the multiplier module 23 .

[0110] Optionally, in this embodiment, the butterfly computing module 22 includes: a first input interface (In0) 221, a first output interface (Out0) 222, a second input interface (In1) 223, and a second output interface (Out1) 224. The connection relationship between each interface and the first FIFO cache module 211, the second FIFO cache module 212, the third FIFO cache module 213, the multiplier module 23, the first external interface 25, and the second external interface 26 in the butterfly computing unit is as follows: Figure 3 As shown:

[0111] The first input interface 221 is connected to the output end of the first FIFO buffer module 211, the output end of the second FIFO buffer module 212 and the input end of the first external interface 25 respectively. The first output interface 222 is connected to the input end of the first FIFO buffer module 211 and the input end of the second external interface 26 respectively.

[0112] Optionally, in this embodiment, the received or sent data is generally complex, and the first input interface 221 will simultaneously receive the real part (re) and the imaginary part (im) of the complex data, and send the real part and the imaginary part to the adder or subtractor correspondingly connected to the butterfly calculation module 22.

[0113] Accordingly, the first output interface 222 will output the real part (re) of the complex data and the imaginary part (im) of the complex data simultaneously according to the correspondingly connected adder.

[0114] The second input interface 223 is respectively connected to the output end of the first FIFO buffer module 211 , the output end of the second FIFO buffer module 212 and the input end of the first external interface 25 , and the second output interface 224 is connected to the input end of the second FIFO buffer module 212 .

[0115] Optionally, the second input interface 223 receives the real part (re) and the imaginary part (im) of the complex data at the same time, and sends the real part and the imaginary part to the subtractor or adder connected to the butterfly calculation module 22 accordingly.

[0116] Accordingly, the second output interface 224 will output the real part (re) of the complex data and the imaginary part (im) of the complex data simultaneously according to the correspondingly connected subtractor.

[0117] In the above embodiment of the present application, the first-in-first-out cache unit includes a first first-in-first-out cache module 211, a second first-in-first-out cache module 212 and a third first-in-first-out cache module 213, and the butterfly calculation module 22 includes a first input interface 221, a first output interface 222, a second input interface 223 and a second output interface 224. Through the connection relationship in this embodiment, the data of the base-two frequency domain extraction fast Fourier transform mode and / or the data of the base-three frequency domain extraction fast Fourier transform mode are all butterfly-operated through the first-in-first-out cache modules in the first-out cache unit, the interfaces in the butterfly calculation module 22 and the multiplier module 23, which further improves the reuse rate of each component, simplifies the structure of the butterfly calculation unit, and thus reduces the consumption of hardware resources for executing a butterfly operation.

[0118] Next, based on the above embodiments, the butterfly computing unit will explain the specific functions of each component through the data flow passing through each component.

[0119] Assume that there are N points of data to be processed, where N represents the number of data, N is an integer power of 2, and the data to be processed is data in the radix-2 frequency domain extraction fast Fourier transform mode. Assume that the calculation stage of the current butterfly calculation unit is m, where m is 1, 2, ..., log2 (N), and the specific value of m is determined by the current butterfly calculation unit according to the pre-set configuration information. One calculation stage only needs to perform one set of butterfly operations and one set of multiplication operations. N points of data to be processed are N / 2 in the mth stage. m The data is divided into a total of 2 m The FIFO_A and the second input interface 223 (In1) of the butterfly computing module 22 are input alternately in groups.

[0120] See also Figure 4 , Figure 4 A schematic diagram of the structure of a butterfly computing unit for performing a radix-2 butterfly operation on data in a radix-2 frequency domain extraction fast Fourier transform mode is provided in an embodiment of the present application. Optionally, the output data at the input end of the first external interface 25 includes at least a first group of data and a second group of data.

[0121] The first external interface 25 sends the first set of data to the first FIFO buffer module 211 , and sends the second set of data to the second input interface 223 of the butterfly calculation module 22 .

[0122] After the first external interface 25 completes sending the group data, the butterfly calculation module 22 receives the first group of data sent by the first first-in-first-out cache module 211, and performs a first butterfly calculation based on the first group of data and the second group of data to obtain first butterfly calculation result data and second butterfly calculation result data, and sends the first butterfly calculation result data to the second external interface 26 through the first output interface 222, and sends the second butterfly calculation result data to the second first-in-first-out cache module 212 through the second output interface 224.

[0123] When the butterfly calculation module 22 completes the first butterfly calculation, the multiplier module 23 starts working, the multiplier receives the second butterfly calculation result data sent by the second first-in-first-out cache module 212, and reads the first rotation factor stored in the rotation factor storage module 24, and performs complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain the first multiplication calculation result data, and sends the first multiplication calculation result data to the third first-in-first-out cache module 213, so that the first multiplication calculation result data is sent to the second external interface 26 through the third first-in-first-out cache module 213, so that the first multiplication calculation result data enters the next butterfly calculation unit through the second external interface 26 for the next stage of calculation, until all groups of data are calculated.

[0124] In the above-mentioned embodiments of the present application, the data of the fast Fourier transform mode is extracted in the radix-2 frequency domain, and the radix-2 butterfly operation is completed through the structure of the butterfly computing unit in the present application. The radix-2 butterfly operation is performed by a simpler butterfly computing unit, which reduces the time for performing the radix-2 butterfly operation and improves the computing efficiency.

[0125] Furthermore, when the data to be processed is data in a base-three frequency domain extraction fast Fourier transform mode, the specific functions of each component in the butterfly computing unit are explained.

[0126] Assume that there are N points of data to be processed, where N represents the number of data, N is an integer power of 2, and the data to be processed is data in the base-three frequency domain extraction fast Fourier transform mode. Assume that the calculation stage of the current butterfly calculation unit is m, where m is 1, 2, ..., log2 (N), and the specific value of m is determined by the current butterfly calculation unit according to the pre-set configuration information. One calculation stage needs to perform three groups of butterfly operations and three groups of multiplication operations, and the three groups of multiplication operations include a group of constant multiplication calculations. The N points of data to be processed are N / 3 in the mth stage. m The data is divided into a total of 3 m The three groups of data are input as one input cycle, and the three groups of data are input to FIFO_B, FIFO_A and the second input interface 223 (In1) of the butterfly calculation module 22 in one input cycle respectively.

[0127] See also Figure 5A , Figure 5A A schematic diagram of the structure of a butterfly computing unit for performing a first set of butterfly operations on data in a base-three frequency domain extraction fast Fourier transform mode is provided in an embodiment of the present application. Optionally, the output data at the input end of the first external interface 25 includes at least a third set of data, a fourth set of data and a fifth set of data.

[0128] The first external interface 25 sends the third set of data to the second FIFO buffer module 212 , sends the fourth set of data to the first FIFO buffer module 211 , and sends the fifth set of data to the second input interface 223 of the butterfly calculation module 22 .

[0129] The butterfly calculation module 22 receives the fourth set of data sent by the first first-in-first-out cache module 211, and performs a second butterfly calculation based on the fourth set of data and the fifth set of data to obtain third butterfly calculation result data and fourth butterfly calculation result data, and sends the third butterfly calculation result data to the first first-in-first-out cache module 211 through the first output interface 222, and sends the fourth butterfly calculation result data to the second first-in-first-out cache module 212 through the second output interface 224.

[0130] The multiplier module 23 receives the fourth butterfly calculation result data sent by the second FIFO buffer module 212, reads the second rotation factor stored in the rotation factor storage module 24, performs constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain the second multiplication calculation result data, and sends the second multiplication calculation result data to the third FIFO buffer module 213. The second rotation factor is a constant, and the constant can be .

[0131] See also Figure 5B , Figure 5B A schematic diagram of the structure of a butterfly computing unit for performing a second set of butterfly operations on data in a base-three frequency domain decimation fast Fourier transform mode provided in an embodiment of the present application.

[0132] The butterfly calculation module 22 receives the third butterfly calculation result data sent by the first FIFO buffer module 211 , and receives the third set of data sent by the second FIFO buffer module 212 .

[0133] A third butterfly calculation is performed according to the third butterfly calculation result data and the third group of data to obtain fifth butterfly calculation result data and sixth butterfly calculation result data.

[0134] The fifth butterfly calculation result data is sent to the second external interface 26 through the first output interface 222 , and the sixth butterfly calculation result data is sent to the second FIFO buffer module 212 through the second output interface 224 .

[0135] See also Figure 5C , Figure 5C A schematic diagram of the structure of a butterfly computing unit for performing a third set of butterfly operations on data in a base-three frequency domain extraction fast Fourier transform mode provided in an embodiment of the present application. When the second set of butterfly operations is completed, the butterfly computing module 22 starts to perform the third set of butterfly operations, and the butterfly computing module 22 receives the sixth butterfly calculation result data sent by the second first-in-first-out buffer module 212, and receives the second multiplication calculation result data sent by the third first-in-first-out buffer module 213.

[0136] A fourth butterfly calculation is performed according to the sixth butterfly calculation result data and the second multiplication calculation result data to obtain seventh butterfly calculation result data and eighth butterfly calculation result data.

[0137] The seventh butterfly calculation result data is sent to the multiplier module 23 through the first output interface 222 , and the eighth butterfly calculation result data is sent to the second FIFO buffer module 212 through the second output interface 224 .

[0138] The multiplier module 23 receives the seventh butterfly calculation result data sent by the butterfly calculation module 22, and reads the third rotation factor stored in the rotation factor storage module 24, performs complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor, obtains third multiplication calculation result data, and sends the third multiplication calculation result data to the third first-in-first-out cache module 213, so that the third multiplication calculation result data is sent to the second external interface 26 through the third first-in-first-out cache module 213.

[0139] The multiplier module 23 is also specifically used to: receive the eighth butterfly calculation result data sent by the second first-in-first-out cache module 212, and read the fourth rotation factor stored in the rotation factor storage module 24, perform complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out cache module 213, so that the fourth multiplication calculation result data is sent to the second external interface 26 through the third first-in-first-out cache module 213.

[0140] In summary, the calculation of three sets of data in one input cycle is completed, and the calculation of three sets of data in the next cycle begins until all data are completed.

[0141] In this embodiment, the structure of performing radix-three butterfly operation in the related art is as follows: Fig. 6A As shown, Fig. 6A Schematic diagram of a radix-three butterfly operation structure in a related art provided by the present application. The radix-three butterfly operation structure in the related art is complex. For three sets of data ( , , ), a complex radix-three butterfly operation is required, and in this embodiment, if Figure 6B As shown, Figure 6B A schematic diagram of a radix-three butterfly operation structure provided in an embodiment of the present application, for three sets of data ( or or ), by dividing it into three structures similar to the radix-2 butterfly operation, and performing three radix-2 butterfly calculations, the calculation result can be obtained.

[0142] In the above embodiment of the present application, the data of the radix-3 frequency domain extraction fast Fourier transform mode is subjected to three butterfly operations through the structure of the butterfly computing unit in the present application, wherein each butterfly operation is similar to the butterfly operation of the data of the radix-2 frequency domain extraction fast Fourier transform mode. Thus, the radix-3 butterfly operation can be performed through the same structure, the reuse rate of each component is improved, the structure of the butterfly computing unit is simplified, and the consumption of hardware resources for executing the radix-3 butterfly operation is reduced.

[0143] The present application also provides a butterfly computing unit array, such as Figure 7 As shown, Figure 7 A structural schematic diagram of a butterfly computing unit array provided in an embodiment of the present application, the butterfly computing unit array includes multiple butterfly computing units, and the multiple butterfly computing units are connected in series. The serial connection may also be referred to as a pipeline structure connection in the present application.

[0144] It can be understood that the number of butterfly computing units is not limited in this embodiment.

[0145] In the above-mentioned embodiment of the present application, by performing radix-2 or radix-3 butterfly operations through a plurality of butterfly computing units connected in series in a butterfly computing unit array, the efficiency of the radix-2 or radix-3 butterfly operations can be effectively improved, thereby reducing the calculation cycle.

[0146] The present application also provides a mixed basis reconfigurable array, which can also be called a coarse-grained reconfigurable array of mixed basis FFT, and includes the butterfly computing unit array in the above embodiment.

[0147] In order to facilitate the understanding of the mixed-radix reconfigurable array in the present application, the mixed-radix reconfigurable array in the related art is described below. The mixed-radix reconfigurable array in the related art is called a mixed-radix FFT processor.

[0148] like Figure 8 As shown, Figure 8 This is a structural diagram of a mixed-radix FFT processor in another related technology provided by the present application. The mixed-radix FFT processor includes a storage unit 81, a control unit 82, a block floating-point unit 83 and an operation unit 84.

[0149] Among them, the operation unit 84 is equivalent to the butterfly computing unit in the present application. The operation unit 84 includes a multiplication unit 841 and a butterfly unit 842. The data parallelism of the operation unit 84 is 16, and at most one radix-16 butterfly operation, two radix-8 butterfly operations, two radix-5 butterfly operations, four radix-4 butterfly operations, four radix-3 butterfly operations, or eight radix-2 butterfly operations can be performed simultaneously.

[0150] The connection relationship is as follows: the storage unit 81 is connected to the operation unit 84 and the control unit 82 respectively, the control unit 82 is also connected to the operation unit 84 , the block floating point unit 83 is connected to the operation unit 84 , and the multiplication unit 841 is connected to the butterfly unit 842 .

[0151] The multiplication unit 841 includes fifteen rotation factor multipliers, and the butterfly unit 842 includes six interleaving modules and five-level operation units, wherein the six interleaving modules are respectively a first interleaving module, a second interleaving module, a third interleaving module, a fourth interleaving module, a fifth interleaving module and a sixth interleaving module. The five-level operation units are respectively a first-level operation unit, a second-level operation unit, a third-level operation unit, a fourth-level operation unit and a fifth-level operation unit. The first-level operation unit is composed of 8 parallel radix-2 butterfly units, the second-level operation unit is composed of 4 parallel radix-2 butterfly units, 4 variable butterfly units and 4 simple multipliers, the third-level operation unit is composed of a parallel simple multiplier, a plurality of complex multipliers and 2 complex adders, the fourth-level operation unit is composed of 8 parallel radix-2 butterfly units, and the fifth-level operation unit is composed of 8 parallel radix-2 butterfly units and 4 simple multipliers.

[0152] It can be seen that although the operation unit in the above-mentioned mixed-base FFT processor can improve the parallelism of data processing by increasing the interleaving module and each level of operation units included in the butterfly unit in the operation unit, it will lead to an increase in the complexity of the overall structure of the mixed-base FFT processor, a low reuse rate of each component, and still a large consumption of hardware resources.

[0153] Therefore, in view of the complex structure of the above-mentioned mixed-radix FFT processor, the mixed-radix reconfigurable array provided in the present application has a simpler structure.

[0154] For details, please see Fig. 9 , Fig. 9 A schematic diagram of the structure of a hybrid-based reconfigurable array provided in an embodiment of the present application, which includes, in addition to a butterfly computing unit array, a memory 91, an input controller 92, an output controller 93 and a timing controller 94.

[0155] The connection relationship can be:

[0156] The memory 91 is connected to the input end of the input controller 92, the input end of the output controller 93 and the input end of the timing controller 94 respectively. The output end of the input controller 92, the input end of the output controller 93 and the output end of the timing controller 94 are connected to the butterfly computing unit array respectively.

[0157] Optionally, the output end of the input controller 92, the input end of the output controller 93 and the output end of the timing controller 94 are respectively connected to a plurality of butterfly computing units in the butterfly computing unit array. Fig. 9 In order to make the drawings clear and to show the connection between all butterfly computing units and the input controller 92, the output controller 93 and the timing controller 94, Fig. 9 The connections shown in the figure do not limit the present application.

[0158] The functions of each component are:

[0159] Optionally, the memory 91 is used to store configuration information. The configuration information may include data to be operated and an operation mode of the data to be operated, and the operation mode includes a radix-2 frequency domain extraction fast Fourier transform mode or a radix-3 frequency domain extraction fast Fourier transform mode.

[0160] Optionally, after the configuration information is loaded into the timing controller 94 , the timing controller 94 may determine the timing logic of each butterfly computing unit in the butterfly computing unit array according to the configuration information.

[0161] Exemplarily, the timing controller 94 may determine the butterfly computing units required for performing butterfly operations in the butterfly computing unit array, and the timing relationship between the butterfly computing units.

[0162] Optionally, after the configuration information is loaded into the input controller 92, the input controller 92 may group the operation data according to the operation mode to obtain multiple groups of data.

[0163] Exemplarily, if the operation mode is a radix-2 frequency domain extraction fast Fourier transform mode, the data to be operated is decomposed into powers of 2 in length to obtain a plurality of grouped data.

[0164] Exemplarily, if the operation mode is the radix-3 frequency domain extraction fast Fourier transform mode, the data to be operated is decomposed into powers of length 3 to obtain a plurality of grouped groups of data.

[0165] Optionally, after the configuration information is loaded into the output controller 93, the output controller 93 may determine the butterfly computing unit at the end point of the final output result data, and receive the output result data of the butterfly computing unit on the data to be operated.

[0166] The mixed-radix reconfigurable array in this embodiment can calculate The fast Fourier transform of the point The following formula needs to be satisfied:

[0167]

[0168] in, and The value can be 0, 1, ... q, Less than or equal to , , and is an exponent whose value is an integer.

[0169] Taking 256 points of data to be processed as an example, the configuration information is first imported into the timing controller 94, the input controller 92, the butterfly computing unit array and the output controller 93. Fig. 9 The first two rows of butterfly computing units in the butterfly computing unit array are configured as circuits for performing 256-point radix 2 DIF-FFT. These eight butterfly computing units complete eight computing stages in sequence, and the last row of butterfly computing units is idle. The input controller 92 first serially inputs the data to be processed into the butterfly computing unit in the first row and the first column, the timing controller 94 generates a timing signal to control the calculation process of the butterfly computing unit, and finally the output controller 93 receives the output result data obtained from the butterfly computing unit in the second row and the fourth column.

[0170] In the above embodiment of the present application, the hybrid basis reconfigurable array includes a butterfly computing unit array, a memory 91, an input controller 92, an output controller 93 and a timing controller 94. Compared with the hybrid basis FFT processor in the related art, the hybrid basis reconfigurable array in the present application has a simpler structure, improves the reuse rate of each component, and thus reduces the resource consumption of hardware.

[0171] In the present application, a chip is also provided, which includes the mixed-base reconfigurable array in the above embodiment to perform FFT calculation on data. The technical effect achieved is similar to that of the above embodiment, and will not be described again to avoid redundancy.

[0172] In the present application, simulation verification is also performed on the data calculated by the butterfly computing unit in the chip of the present application.

[0173] This application describes the butterfly computing unit in Verilog language. A butterfly computing unit is used as a level (computation stage) in FFT calculation. By verifying it on a preset platform, the resource usage shown in Table 1 is obtained.

[0174] Table 1

[0175]

[0176] For example, the data to be processed is 288 data points. When performing the FFT calculation task of 288 data points, a total of 7 levels of calculation are required. , that is, the first two levels are implemented by radix-3 butterfly operations, and the last five levels are implemented by radix-2 butterfly operations.

[0177] By simulating and calculating the 288-point fast Fourier transform in the preset circuit drawing software, the calculation results are as follows Fig.10 As shown, Fig.10A schematic diagram of a calculation result provided in an embodiment of the present application, wherein the horizontal axis X represents the frequency and the vertical axis Y represents the amplitude. When X is 7, Y is 130.061, and when X is 283, Y is 130.086.

[0178] In the preset data analysis software, the 288-point fast Fourier transform is simulated and calculated, and the calculation results are as follows Fig.11 As shown, Fig.11 Another schematic diagram of calculation results provided by the embodiment of the present application, wherein the horizontal axis X represents the frequency and the vertical axis Y represents the amplitude. When X is 7, Y is 130.598, and when X is 283, Y is 130.598.

[0179] contrast Fig.10 and Fig.11 It can be seen that the peak value of the result obtained by the preset circuit drawing software simulation calculation and the difference between the result calculated by the preset data analysis software are both within the preset error threshold range, meeting the index requirements of FFT calculation.

[0180] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0181] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A butterfly computing unit, characterized in that: include: A first-in-first-out cache unit, a butterfly calculation module, a multiplier module, a rotation factor storage module, a first external interface and a second external interface; The first-in-first-out cache unit is connected to the butterfly calculation module, the multiplier module, the first external interface and the second external interface respectively, the butterfly calculation module is connected to the multiplier module, and the multiplier module is connected to the rotation factor storage module and the second external interface; A first external interface is used to input data in a radix-2 or radix-3 frequency domain extraction fast Fourier transform mode, wherein the data in the radix-2 and radix-3 frequency domain extraction fast Fourier transform mode both include multiple groups of data; The first-in-first-out cache unit is used to cache at least one set of data or the butterfly calculation result data output by the butterfly calculation module or the multiplication calculation result data output by the multiplier module; The butterfly calculation module is used to receive the data output by the first-in first-out cache unit, and perform butterfly calculation on the data output by the first-in first-out cache unit to obtain butterfly calculation result data; The multiplier module is used to obtain the rotation factor from the rotation factor storage module, and perform multiplication calculation on the butterfly calculation result data output by the first-in first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain the multiplication calculation result data; The second external interface is used to send out the multiplication result data.

2. The butterfly computing unit according to claim 1, characterized in that: The first-in-first-out cache unit includes: a first first-in-first-out cache module, a second first-in-first-out cache module and a third first-in-first-out cache module; The first FIFO cache module input end is respectively connected to the butterfly computing module output end and the first external interface input end, and the first FIFO cache module output end is connected to the butterfly computing module input end; The second FIFO buffer module input end is respectively connected to the butterfly calculation module output end and the first external interface input end, and the second FIFO buffer module output end is respectively connected to the butterfly calculation module input end and the multiplier module input end; The input end of the third FIFO buffer module is connected to the output end of the multiplier module, and the output end of the third FIFO buffer module is respectively connected to the input end of the butterfly calculation module and the input end of the second external interface.

3. The butterfly computing unit according to claim 2, characterized in that: The butterfly computing module includes: a first input interface, a first output interface, a second input interface and a second output interface; The first input interface is respectively connected to the first FIFO buffer module output end, the second FIFO buffer module output end and the first external interface input end, and the first output interface is respectively connected to the first FIFO buffer module input end and the second external interface input end; The second input interface is connected to the output end of the first FIFO buffer module, the output end of the second FIFO buffer module and the input end of the first external interface respectively, and the second output interface is connected to the input end of the second FIFO buffer module.

4. The butterfly computing unit according to claim 3, characterized in that: The output data of the first external interface input terminal at least includes a first group of data and a second group of data, wherein the first group of data and the second group of data are data in a base-2 frequency domain decimation fast Fourier transform mode; The first external interface is specifically used to: send the first set of data to the first first-in first-out cache module, and send the second set of data to the second input interface of the butterfly calculation module; The butterfly calculation module is specifically used to: receive the first group of data sent by the first first-in-first-out cache module, and perform a first butterfly calculation according to the first group of data and the second group of data to obtain first butterfly calculation result data and second butterfly calculation result data, and send the first butterfly calculation result data to the second external interface through the first output interface, and send the second butterfly calculation result data to the second first-in-first-out cache module through the second output interface; The multiplier module is specifically used to: receive the second butterfly calculation result data sent by the second first-in-first-out cache module, read the first rotation factor stored in the rotation factor storage module, and perform complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain first multiplication calculation result data, and send the first multiplication calculation result data to the third first-in-first-out cache module, so that the first multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

5. The butterfly computing unit according to claim 3, characterized in that: The output data of the first external interface input terminal at least includes a third group of data, a fourth group of data and a fifth group of data, wherein the third group of data, the fourth group of data and the fifth group of data are data in a base-three frequency domain decimation fast Fourier transform mode; The first external interface is specifically used to: send the third group of data to the second first-in first-out cache module, send the fourth group of data to the first first-in first-out cache module, and send the fifth group of data to the second input interface of the butterfly calculation module; The butterfly calculation module is specifically used to: receive the fourth group of data sent by the first first-in-first-out cache module, and perform a second butterfly calculation according to the fourth group of data and the fifth group of data to obtain third butterfly calculation result data and fourth butterfly calculation result data, and send the third butterfly calculation result data to the first first-in-first-out cache module through the first output interface, and send the fourth butterfly calculation result data to the second first-in-first-out cache module through the second output interface; The multiplier module is specifically used to: receive the fourth butterfly calculation result data sent by the second first-in-first-out cache module, read the second rotation factor stored in the rotation factor storage module, perform constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain second multiplication calculation result data, and send the second multiplication calculation result data to the third first-in-first-out cache module.

6. The butterfly computing unit according to claim 5, characterized in that: The butterfly computing module is also specifically used for: receiving the third butterfly calculation result data sent by the first first-in-first-out buffer module, and receiving the third set of data sent by the second first-in-first-out buffer module; Perform a third butterfly calculation according to the third butterfly calculation result data and the third group of data to obtain fifth butterfly calculation result data and sixth butterfly calculation result data; The fifth butterfly calculation result data is sent to the second external interface through the first output interface, and the sixth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

7. The butterfly computing unit according to claim 6, characterized in that: The butterfly computing module is also specifically used for: receiving the sixth butterfly calculation result data sent by the second FIFO buffer module, and receiving the second multiplication calculation result data sent by the third FIFO buffer module; Performing a fourth butterfly calculation according to the sixth butterfly calculation result data and the second multiplication calculation result data to obtain seventh butterfly calculation result data and eighth butterfly calculation result data; The seventh butterfly calculation result data is sent to the multiplier module through the first output interface, and the eighth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

8. The butterfly computing unit according to claim 7, characterized in that: The multiplier module is further specifically used for: Receiving the seventh butterfly calculation result data sent by the butterfly calculation module; Read the third rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor to obtain third multiplication calculation result data, and send the third multiplication calculation result data to the third first-in-first-out cache module, so that the third multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

9. The butterfly computing unit according to claim 8, characterized in that: The multiplier module is further specifically used for: receiving the eighth butterfly calculation result data sent by the second first-in-first-out cache module; Read the fourth rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out cache module, so that the fourth multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

10. A butterfly computing unit array, characterized in that: It comprises a plurality of butterfly computing units as described in any one of claims 1 to 9, wherein the plurality of butterfly computing units are connected in series.

11. A hybrid-based reconfigurable array, characterized in that: Comprising the butterfly computing unit array as claimed in claim 10.

12. The hybrid-based reconfigurable array according to claim 11, characterized in that: Also includes: Memory, input controller, output controller and timing controller; The memory is connected to the input controller input terminal, the output controller input terminal and the timing controller input terminal respectively, and the input controller output terminal, the output controller input terminal and the timing controller output terminal are connected to the butterfly computing unit array respectively; The memory is used to store configuration information, the configuration information includes data to be operated and an operation mode of the data to be operated, the operation mode includes a base-2 frequency domain extraction fast Fourier transform mode or a base-3 frequency domain extraction fast Fourier transform mode; The timing controller is used to determine the timing logic of each butterfly computing unit in the butterfly computing unit array according to the configuration information; The input controller is used to group the data to be operated according to the operation mode to obtain multiple groups of data; The output controller is used to receive output result data of the butterfly computing unit array on the data to be calculated.

13. The hybrid-based reconfigurable array according to claim 12, characterized in that: The input controller output terminal, the output controller input terminal and the timing controller output terminal are respectively connected to a plurality of the butterfly computing units in the butterfly computing unit array.

14. A chip, characterized in that: Comprising a hybrid-based reconfigurable array as described in any one of claims 11-13.

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