Multi-core package-level system based on core particle framework and task mapping method thereof for core particles

Abstract

The invention discloses a multi-core package-level system based on a core particle framework and a task mapping method for core particles. The system comprises a core unit, a core particle unit and apackaging unit; the core unit comprises a plurality of parallel processing units and an L1 local buffer unit shared by the plurality of processing units; the L1 local buffer unit is only used for storing weight data; the core particle unit comprises a plurality of parallel core units and an L2 shared buffer unit shared by the plurality of core units; the L2 shared buffer unit is only used for storing activation data; the package unit includes a plurality of parallel and interconnected core grain units, and a DRAM memory shared by the plurality of core grain units. According to the method, scheme search is carried out through core particle Chiplet calculation mapping, calculation mapping between core particle Chiplets, a data distribution template of PE array calculation mapping in the coreparticle Chiplets and scale distribution of calculation of each layer, so that less inter-chip communication, less on-chip storage and less DRAM access are achieved.

Description

technical field [0001] The invention relates to a multi-core chip system and a mapping method, in particular to a high-efficiency task mapping and scheduling method of a deep neural network oriented to a core particle architecture and system. Background technique [0002] With the continuous reduction of chip manufacturing size, the development progress of Moore's law, which relies on size reduction, has slowed down, and the cost of advanced process nodes is very high. Therefore, it is necessary to control the area of ​​the chip under the advanced process node. Ten years ago, due to the existence of "power consumption wall", the design of processors migrated from increasing the main frequency to multi-core design; now, due to the existence of "cost wall", the design of processors needs to migrate from increasing integration density to multi-chip Encapsulation scheme. [0003] In order to solve the problem of "cost wall", chiplet (Chiplet) technology came into being. Chipl...

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Problems solved by technology

The former has a large routing delay problem, and the latter cannot avoid the problem of access conflicts leading to a decrease in bandwidth efficiency

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