Compression generation method for testing data of digital integrated circuit

Abstract

The invention discloses a compression generation method for testing data of a digital integrated circuit. Differing from a traditional testing method, the method comprises the following steps of: firstly analyzing a kind of a single input change testing sequence with linear relation; confirming a testing pattern set with a new trouble detecting capacity by a fault simulation method; considering values of a small part bit of the testing pattern set compressed by the linear relation is a compressed testing pattern set; and storing the compressed testing pattern set in automatic testing equipment (ATE). During testing application, the compressed testing pattern set is decompressed by a hardware circuit according to linear relation which is defined in advance so that an actual testing pattern set is restored. Besides, the actual testing pattern set is applied to a tested circuit. The data volume stored in the ATE is less than the data volume of the actual testing pattern set. The testing method has the characteristics of high compression ratio, easy realization, low power consumption and high coverage rate.

Description

technical field [0001] The invention relates to an integrated circuit test method, in particular to a method for generating digital integrated circuit test data with a high compression rate. Background technique [0002] After the feature size of integrated circuits entered the nanometer stage, the integration, complexity, and operating speed of digital circuits and systems continued to increase. Traditional fault models and testing methods have been difficult to deal with. The prominent problems are mainly manifested in: [0003] 1). The amount of test data is increasing, but the number of I / Os of the chip, the number of channels of the automatic test equipment ATE (Auto-Test Equipment, referred to as ATE), the data storage capacity and the working speed are limited, resulting in the test time is also increasing. The longer it is, the more expensive it is to test. [0004] 2) The average power consumption and peak power consumption of the tested circuit CUT (Circuit Under ...

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Problems solved by technology

[0005] 3) The number of units in the system-on-chip SOC (System On Chip, SOC for short) and system-in-package SIP (System In Package, SIP for short) is huge, and the test complexity and difficulty are getting higher and higher

[0006] 4) The size of CMOS circuits continues to decrease, causing a sharp increase in defects and soft errors in the circuits

[0036] An effective way to reduce the amount of test data is to compress it. The traditional test data compression is to compress the generated test pattern, and the compression rate is not high.

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