Test pattern generator of integrated circuit and test method thereof

Abstract

The invention relates to the test field of integrated circuits and discloses a low power consumption test pattern generator of an integrated circuit and a test method thereof. The low power consumption test pattern generator of the integrated circuit is based on a restructurable Johnson counter; compared with a traditional test pattern generator, the low power consumption test pattern generator can ensure that a generated test sequence can simultaneously reduce the test pattern conversion times in a space domain and a time domain, has low test pattern generation frequency in the space domain and generates different single-input changed sequences to each scan chain in the time domain, thereby greatly lowering the power consumption of a combined logic circuit part of a tested integrated circuit and the scan power consumption of the scan chain.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to an integrated circuit low power consumption test pattern generator (Reconfigurable Johnson-Linear Feedback Shift Register TPG, RJ-LFSR type TPG for short) and a testing method thereof. The IC's low-power test pattern generator is based on a Reconfigurable Johnson Counter. Background technique [0002] The test pattern generator (TPG for short) in the built-in-self-test (Built-in-Self Test, BIST) structure of integrated circuits is generally implemented by a linear feedback shift register (Linear Feedback Shift Register, LFSR for short). . The current test method combining BIST structure and scan design can reduce test complexity and test cost. However, this test method will increase the internal node jumps of the circuit under test, thereby increasing the test power consumption. An increase in average power consumption or peak power consumption will lead to a decrease...

AI Technical Summary

Problems solved by technology

The SIC sequence can minimize the input transitions, thereby reducing the internal circuit transition activity. The disadvantage of the existing method is that the SIC sequence generator will cause an increase in hardware overhead and delay.

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