System for testing system internuclear wiring fault on integrated circuit chip and method thereof

Abstract

The invention relates to a system for testing a system internuclear wiring fault on an integrated circuit chip and a method thereof. The system comprises a circuit structure which is added for perfecting the IP internuclear wiring fault test and the IP intranuclear fault test in a system on the integrated circuit chip and a test inquiring mechanism which runs on the basis of the circuit structure. The invention can test the IP internuclear wiring of the system on the integrated circuit chip. The fault types of the test comprises the solid-zero fault, the solid-solid fault, the open circuit fault, the short circuit fault, the delaying fault and the noise fault. By adding a hardware structure, the invention decomposes a scanning chain of edge packing units, thereby making the best of a test buss and shortening the test time; with the output type edge packing unit, the invention automatically generates a test vector; with the input type edge packing unit, the invention further shortens the test time. The structure is compatible with the intranuclear test structure, thereby realizing the higher flexibility, making the best of the test resource, and further improving the fault coverage rate of the system of the whole integrated circuit chip. The invention is simple in circuit structure, convenient in test inquiring mechanism, and suitable for the various systems on the integrated circuit chips which are designed and built with the IP multiplexing technology.

Description

technical field The invention relates to an integrated circuit fault testing system and method, in particular to a testing system and method for inter-core connection faults applied to an integrated circuit system on chip (SOC System on a Chip). Background technique Now integrated circuit (IC) designers are developing towards better cost advantages and time-to-market, and seize market opportunities with the fastest speed and the best cost performance. The existence of these needs urgently makes multiple functions integrated into one chip. become possible, the system on a chip (SOC System on a chip) came into being. From an engineering point of view, integrating more functions into a single chip can indeed achieve cost savings, but from a testing point of view, a large number of SOC pins, multiple cores with different Features such as test vectors make the test of SOC much more complicated than that of a single chip. How to reduce the test difficulty and test cost of SOC ha...

AI Technical Summary

Problems solved by technology

The current research on SOC connection fault testing mainly focuses on the optimization algorithm of vector compression and test structure, but the hardware structure of the test system and the test search mechanism are not involved, and there is no research on the inter-core connection fault and the core fault test. consider together

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