Scan test latch macrocell and scan test method

Abstract

The invention provides a scan test latch macrocell and a scan test method. According to the scan test method, through a customized scan test macrocell, an ATPG test vector, based on a structure, used for a latch unit can be generated with a common scan test design method for a D trigger according to a special design process, the problems that testability design development cannot be easily performed on an existing digital special integrated circuit based on latch design, the fault coverage rate of the test vector is low, and time sequence analysis is complex are solved, the fault coverage rate of chip tests is substantially increased, the effectiveness and the completeness of the chip tests are guaranteed, and the method is mainly applied to the test vector development of the digital special integrated circuit based on latch design.

Description

technical field [0001] The invention relates to a scan test macro unit and a scan test method, in particular to a scan test latch macro unit and a scan test method, which belong to the field of design and test of semiconductor digital integrated circuits, and are mainly used in the structuring of semiconductor digital integrated circuits Testing process. Background technique [0002] With the continuous development and progress of semiconductor digital integrated circuits, how to fully and effectively implement digital integrated circuits with an increasing scale of millions of gates, tens of millions of gates, or even larger scales with reasonable time and cost Testing has gradually become one of the most difficult and time-consuming design tasks. When the circuit scale exceeds 100,000 gates, the development time of hand-written (function-oriented) test vectors will exceed the design time of the actual device itself. Therefore, design for test technology (Design For Test,...

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the technology of the present invention is: to overcome the deficiencies in the fault coverage and design complexity of the existing latch-based testability design method, and propose a scan test latch macrocell and a scan test method , the invention is aimed at the Mux-Scan scan test of the latch unit, which can not only use the existing scan test methodology and EDA tools for the D flip-flop unit, simplify the design process, but also ensure a very high fault coverage

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