Multicore processor test method

Abstract

In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently. A processor comprises a plurality of logic block circuits, plurality of logic block circuits comprising at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits, the processor further comprising, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is related to and claims priority to Japanese Application No. 2004-127216 filed Apr. 22, 2004 in the Japanese Patent Office, the contents of which are incorporated by reference herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to processors such as a CPU (Central Processing Unit), MPU (Micro Processing Unit), DSP (Digital Signal Processor) or GPU (Graphics Processing Unit: graphics processor, or image processing LSI or geometry engine), comprising a plurality of execution units (hereinafter referred to simply as “cores”), and to testing methods for such processors. [0004] 2. Description of the Related Art [0005] Conventionally, in computer systems, such as servers, where especially high processing capacity is required, such as for the primary business processing of an enterprise, improvements in processing capacity have been achieved by connecting a plurality of pro...

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Benefits of technology

[0052] According to the present invention, as described above, providing an independent MISR test pattern compression circuit for each logi...

Problems solved by technology

However, with loose coupling using a cluster configuration, communication overhead between the server nodes becomes a problem, while in the case of close coupling using SMP, complexity of the server hardware becomes a problem, and in both cases, with conventional architecture, there is a limit to the performance improvement that could be achieved on a single computer system.

However, in the case of multicore configurations such as CMP, contrary to the improvements in processing performance achieved by increasing the number of cores, there are problems such as increasing complexity of control due to installation of a plurality of cores and lower yields during semiconductor manufacturing due to increased die size.

The reduced yields during semiconductor manufacturing due to the increased die size are a particularly important problem for multicore processors such as CMPs comprising a multicore.

However, with the increasing scale of LSI logic, such as processors manufactured to a high scale of integration by recent ultramicro processes, it has become impossible to disregard the scale of the test pattern size.

Increased test pattern size not only affects prod...

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