20 results about "Pattern size" patented technology

The application provides a phase shift mask and a manufacturing method thereof. In the application, a second key pattern size corresponding to a second photoetching process is obtained, and a second photoetching machine is obtained according to the second key pattern size. The resolution identification ability of the obtained second photoetching machine is matched with the second key pattern size, so that the problem that the resolution ability of the photoetching machine used in the second photoetching process is not enough and the formed phase shift mask is defective is avoided, and the quality of the phase shift mask is improved.

The invention discloses a micro-nano pattern processing method, which comprises the following steps of: 1, pretreating a pattern electrode and a base material, preparing the pattern electrode matched with the outline of a micro-nano pattern to be processed, performing surface activation treatment, and performing cleaning and modification treatment on the base material; step two, functional material selection and pretreatment: selecting at least two functional materials, and performing dispersion and filtration treatment to form a stable functional material dispersion system; the method has the beneficial effects that synchronous loading of multiple functional materials is achieved through the electrostatic adsorption principle, multi-material micro-nano patterns can be prepared through one-time machining, and compared with a traditional step-by-step machining method, the machining efficiency is improved, and the machining period is remarkably shortened; the precise transfer device and the visual positioning module are adopted, precise alignment of a preformed pattern and a base material is achieved, the pattern size precision can reach the nanoscale, and the problem that in traditional multi-material machining, the alignment precision is low is solved.

The present application relates to the field of integrated circuit manufacturing, and particularly relates to a mask process correction method, device, equipment and storage medium, wherein a target mask pattern and a corresponding design thickness are received; the target mask pattern is input as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; mask layer bottom simulation pattern sizes and mask layer top simulation pattern sizes corresponding to each edge section in the simulation electron beam exposure pattern are determined, to obtain corresponding side wall included angles; size-included angle comparison data groups corresponding to each edge section are determined according to the mask layer bottom simulation pattern sizes, to obtain included angle offset amounts; a target size offset amount is further determined; and the positions of the corresponding edge sections in the mask layer bottom simulation pattern are adjusted according to the target size offset amount. The similarity between the wafer pattern obtained by performing a photolithography process on the mask layer corrected by the present application and the photolithography target pattern is greatly improved.

The invention discloses a method for selectively regulating and controlling the size of a pattern through a low-temperature ion implantation process, and belongs to the technical field of integrated circuit manufacturing. Performing low-temperature ion implantation on the intermediate material to generate a modified layer on the vertical side wall of the non-hollow part of the intermediate film layer; selective growth is carried out through atomic layer deposition, a deposition layer covering the surface of the intermediate material is formed, the deposition layer forms an adjusted pattern structure, and the profile of the adjusted pattern structure is reduced relative to that of the intermediate pattern structure; part of the deposition layer is removed through wet etching, so that the upper part of the bottom film layer is exposed; performing thermal annealing treatment; and transferring the adjusted pattern structure to the bottom film layer through dry etching. According to the invention, the feature size of the pattern structure can be accurately controlled and reduced, the side wall of the pattern structure can obtain a flatter surface appearance without defects, and the performance of a semiconductor device can be improved.

A pattern size compensation method and system, device, storage medium and computer program product, the method comprising: providing a design layout of a plurality of chip units, the design layout comprising a plurality of design patterns, the plurality of chip units forming an exposure unit, the exposure unit being an exposure area divided on a wafer; obtaining the pattern density distribution condition of each chip unit by taking the whole design patterns of the plurality of chip units in the exposure unit as a calculation reference; and according to the pattern density distribution condition of the chip unit, performing pattern size compensation on the design pattern of the chip unit to obtain a compensation pattern. According to the invention, accurate graph size compensation can be realized.

This invention provides a method and system for measuring the size of a lens pattern. [Solution] The method includes the steps of: using a printing module to form a lens including a pattern; using a camera module to acquire a lens image of the lens including the pattern, wherein the lens image includes a pattern image portion corresponding to the pattern; providing an annular mask unit on the lens image, wherein the annular mask unit covers the pattern image portion; and using an image analysis unit to perform at least one of steps (a) and (b), wherein step (a) is the step of determining an inner circle on the pattern image portion and calculating the diameter of the inner circle, and step (b) is the step of determining an outer circle on the pattern image portion and calculating the diameter of the outer circle, wherein the image analysis unit is connected to the camera module.

The invention provides an exposure control method and device of a photoetching machine, equipment and a storage medium, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: before exposure is started, controlling a preheating device to heat a photomask of a photoetching machine, so that the photomask reaches a maximum deformation value after being heated; transferring the heated photomask into a photoetching machine, and exposing the test wafer by adopting the heated photomask according to preset exposure parameters; obtaining a pattern size deviation between an exposure pattern on the test wafer and a preset pattern of the photomask; adjusting a preset exposure parameter according to the pattern size deviation; and in the exposure process, exposing the wafer to be processed by adopting the heated photomask according to the adjusted exposure parameters. The invention ensures that the dimensional deviation between the wafer exposure pattern and the photomask preset pattern is stable and controllable, improves the process stability, and does not need to pause to wait for the photomask to cool in continuous exposure, thereby shortening the exposure time of each wafer and improving the productivity of a photoetching machine.

The invention provides an auxiliary graph adding method and system and a layout, and belongs to the field of semiconductors. The auxiliary graph adding method comprises the following steps: providing a layout, dividing the layout into a plurality of areas, adding a second auxiliary graph on one side, far away from the main graph, of the first auxiliary graph, and adjusting parameters of the second auxiliary graph until the graph density of the target area is within a target threshold range, the minimum distance between the second auxiliary graph and the main graph meets a set value. According to the invention, the second auxiliary pattern is added, and the minimum distance between the second auxiliary pattern and the main pattern meets the set value, so that the second auxiliary pattern cannot be imaged and does not influence the key size of the main pattern, thereby reducing the load effect, avoiding the influence on the pattern size uniformity, and improving the problem of non-uniform pattern density in the layout. Especially for a low-density graph area in the layout, the light transmittance distribution of the area is ensured to be uniform, and the problem of non-uniform imaging is reduced.

The invention provides a wafer processing method and device, equipment and a storage medium, and relates to the technical field of semiconductor manufacturing. The wafer processing method comprises the following steps: acquiring machine state data of an etching machine; determining a to-be-operated target etching reaction chamber and a to-be-operated target photoetching machine based on the machine state data; determining a target compensation parameter from a plurality of preset compensation parameters according to the target etching reaction cavity and the target photoetching machine; receiving a wafer to be processed; the target photoetching machine is adopted to conduct photoetching processing on the wafer to be processed, and the target compensation parameters are used for conducting reverse compensation on the graph size of a device to be formed on the wafer to be processed in the photoetching process; and carrying out etching treatment on the photoetched wafer by adopting the target etching reaction cavity to obtain an etched wafer. According to the method, the target compensation parameter is determined from the plurality of preset compensation parameters, so that accurate reverse compensation can be carried out aiming at the condition of non-uniform circuit size caused by the target etching reaction cavity, and the circuit size in the etched wafer is ensured to be uniform.

This application relates to a method, apparatus, device, medium, and program product for photomask data processing. The method includes: acquiring current photomask design data; processing the current photomask design data to obtain pattern density information and pattern size information for each target region; generating a heat map characterizing the defect degree of each target region; acquiring target regions with defect degrees greater than or equal to a defect threshold; determining defect classification for the target regions based on the pattern density information and pattern size information; when the defect classification includes pattern density classification, acquiring the target area of ​​the target region; when the target area is greater than an area threshold, identifying functional regions of the target region and extracting key signal paths within the functional regions; determining splitting boundaries based on the functional regions and key signal paths; and adjusting the current photomask design data based on the splitting boundaries. This method allows for pre-optimization of the photomask design data.

The present application provides a method and system for measuring a contact lens pattern size. The method for measuring a contact lens pattern size comprises: providing a lens having a pattern; capturing the lens having the pattern using a camera module to generate a lens image, wherein the lens image comprises a pattern image portion corresponding to the pattern; setting a ring mask unit on the lens image, wherein the ring mask unit covers the pattern image portion; using an image analysis unit to perform at least one of steps (a) and (b): (a) determining an inscribed circle of the pattern image portion and calculating a diameter of the inscribed circle, (b) determining a circumscribed circle of the pattern image portion and calculating a diameter of the circumscribed circle, wherein the image analysis unit is coupled to the camera module.

This disclosure provides a display device including a display panel with pixels and an optical improvement layer on the display panel. The optical improvement layer includes a first pattern layer and a second pattern layer that overlap each other. The first pattern layer has a first refractive index, and the second pattern layer has a second refractive index different from the first refractive index. The first pattern layer has an average pattern size larger than that of the second pattern layer, and the average pattern ratio of the patterns included in the first pattern layer is less than the average pattern ratio of the patterns included in the second pattern layer. Furthermore, another embodiment of this disclosure provides an optical improvement layer.

Discussed is a display apparatus including a display panel having pixels, and an optical improvement layer on the display panel. The optical improvement layer includes a first pattern layer and a second pattern layer overlapping each other. The first pattern layer has a first refractive index, the second pattern layer has a second refractive index different from that of the first refractive index, the first pattern layer has an average pattern size greater than that of the second pattern layer, and an average of pattern ratios of patterns included in the first pattern layer is smaller than an average of pattern ratios of patterns included in the second pattern layer.

A layout modification method, a storage medium and a terminal, the method comprising: providing an initial layout, including a plurality of first type patterns and a plurality of second type patterns, the first type patterns being parallel to a first direction, the second type patterns penetrating the first type patterns along a second direction, the initial layout including a plurality of pattern areas and non-pattern areas, the first type patterns being located in the pattern areas; allocating the plurality of first type patterns to at least one first layout, the first layout including a plurality of first patterns; obtaining a target pattern area from the initial layout or the first layout, the target pattern area including a preset number of first type patterns or a preset number of first patterns; generating a preset number of sacrifice patterns and cutting patterns on both sides of the target pattern area along the second direction, the sacrifice patterns being parallel to the first type patterns, the cutting patterns being parallel to the first type patterns, the sacrifice patterns being located in the area range of the cutting patterns; and allocating the cutting patterns and the plurality of second type patterns to at least one second layout. The layout modification method has good uniformity of developed pattern size.

A display device is under discussion, comprising a display panel with pixels and an optical enhancement layer on the display panel. The optical enhancement layer contains a first pattern layer and a second pattern layer that overlap. The first pattern layer has a first refractive index, the second pattern layer has a second refractive index different from the first, the first pattern layer has an average pattern size larger than that of the second pattern layer, and the average pattern ratios of the patterns contained in the first pattern layer are smaller than the average pattern ratios of the patterns contained in the second pattern layer.

This application provides a method for fabricating high-resolution patterns and a nanoimprint pattern master. This method utilizes the high selectivity and directionality of deep silicon etching technology and the high-step coverage of thin-film deposition processes. By depositing thin films within the pattern gaps, the pattern size is reduced. This allows for obtaining higher resolution and smaller-sized nanoimprint patterns without increasing the resolution of electron beam lithography itself. Furthermore, by modifying the etching and thin-film deposition parameters, different morphologies of the nanoimprint master and the size of the master pattern can be controlled, resulting in nanoimprint patterns with different feature sizes. Moreover, the fabrication method of this application obtains size-adjustable nanoimprint patterns without changing the mask, requiring only one mask, greatly simplifying the process and reducing costs.

This invention relates to a method for fabricating diffractive optical elements by controlling the thickness of the residual adhesive layer using a template. The method includes the following steps: establishing a structural compensation relationship between the template and the diffractive optical element; determining the etching rate of the residual adhesive layer and the pattern size on the template surface based on the diffraction grating dimensions of different zones of the diffractive optical element, and forming the template; using the template to imprint the pattern onto an imprintable medium, pressing an inorganic dielectric substrate onto the surface of the imprintable medium, allowing the imprintable medium to solidify, demolding, and detecting the thickness of the residual adhesive layer on the minimum duty cycle zone; and simultaneously etching the imprintable medium in different zones according to the etching time and etching rate to simultaneously complete the etching of the residual adhesive layer. This invention compensates for the residual adhesive layer structure by controlling the template, solving the problem of inconsistent residual adhesive layer processing in existing imprint-to-etch methods. It can simultaneously etch the residual adhesive layer in different zones without changing the linewidth of the structural region, resulting in high processing reliability and suitability for industrial applications.

The application discloses a method for selective deposition to realize pattern feature size reduction, comprising the following steps: (1) surface activation, placing a substrate in a reaction cavity, and forming reaction sites on the substrate surface by using plasma; wherein the substrate has a patterned surface, including a first surface and a second surface; the first surface is a photoresist layer; and the second surface is one or more of a dielectric layer, a metal layer, a bottom anti-reflection layer and a mask layer; (2) deposition, introducing monomers into the reaction cavity, and forming a film layer on the first surface by polymerization reaction between the monomers and the reaction sites; and (3) repeating steps (1) and (2) in proportion until target feature sizes are formed on the substrate. The selective deposition of the application can produce epitaxial growth parallel to the plane, so that the pattern size is reduced; the selective deposition method of the application realizes high-precision control of the target size of the photoresist pattern, is suitable for various monomers, is simple in process and high in compatibility.

The application discloses a printing pattern scaling method and device of a conical bottle, an electronic device and a storage medium, relates to the field of conical glass bottle printing, and has the technical features that the printing machine body is used for printing correction of the conical glass bottle, the printing machine body drives the conical glass bottle to rotate to complete printing through gear transmission, gear parameters in transmission and the first printing pattern size of a drawing are acquired, the rotation angle of the gear is calculated according to the gear parameters and the first printing pattern size, the rotation angle of the conical glass bottle is calculated according to the rotation angle of the gear, and the size of the conical glass bottle is acquired. The technical problem that when the conical glass bottle is printed, the radius of the gear division circle is inconsistent with the radius of the conical glass bottle, the length of the movement track of the two is inconsistent when the gear drives the conical glass bottle to rotate by the same angle, a square pattern is printed in a trapezoidal shape, and the pattern is deformed.