Serial transmission chip test method, serial transmission chip test system and integrated chip

Abstract

The invention is applicable to the field of chip test and provides a serial transmission chip test method. The method comprises the following steps: receiving test information sent by a test host through a serial bus, wherein the test information includes the number of a to-be-tested module, the address of a to-be-tested module register, reading and writing control commands and control data; carrying out asynchronous processing and serial-parallel conversion on the received test information and storing the converted test information; and writing the control data into the to-be-tested module register through a bus inside a chip according to the writing control command and the address of the to-be-tested module register, or reading data from the to-be-tested module register through the bus inside the chip according to the reading control command and the address of the to-be-tested module register and sending the read data to the test host through a serial mode after test information receiving is completed. Therefore, multiple logical units can be tested at the same time, the number of chip I / Os is reduced, and the test time is saved.

Description

technical field [0001] The invention relates to the testing field, and more specifically relates to a serial transmission chip testing method, system and integrated chip. Background technique [0002] In the current integrated circuit design, design for testability has become an important part of the design process. The logic units integrated in the chip, such as microprocessors, memories, and digital signal processors, generally have self-built test modules, and need to be tested Some important analog units inside the chip are tested, etc. The commonly used method is to set multiple working modes for the chip, and connect the test pins to the chip I / O through JTAG (Joint Test Action Group; Joint Test Action Group) Above, test in each mode separately. [0003] The above reasons not only lead to an increase in the number of chip I / Os, but also lead to a larger and larger number of total test vectors when testing a single chip, which leads to the fact that in the integrated c...

AI Technical Summary

Problems solved by technology

[0003] The above reasons not only lead to an increase in the number of chip I / Os, but also lead to a larger and larger number of total test vectors when testing a single chip, which leads to the fact that in the integrated circuit design, the test cost occupies the chip An increasing proportion of the cost

The test cost is directly proportional to the test time, that is, the longer the test time of a single chip, the higher the test cost

Existing test solutions require multiple test modes, multiple test pins, low frequency, and cannot test multiple logic units at the same time

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