Successive-approximation type digital-analog converter with feedback advanced setting, and corresponding Delta-Sigma ADC configuration

Abstract

The invention discloses a successive-approximation type digital-analog converter with feedback advanced setting in a Delta-Sigma ADC configuration. The digital-analog converter is characterized in that the digital-analog converter is used for feeding back an output signal of a quantizer to an output node of a second-stage integrator, thereby completing the non-zero loop delay compensation and noise coupling; the digital-analog converter comprises two DAC capacitor arrays in the same structure; each DAC capacitor array comprises a plurality of capacitors in parallel connection; one end of each capacitor of each DAC capacitor array is connected with a VDD or VSS through an independent switch; the other end of each capacitor in one DAC capacitor array is connected to a link of an input Vinp and the positive input end Vp of a dynamic comparator, and the other end of each capacitor in the other DAC capacitor array is connected to a link of an input Vinn and the negative input end Vn of the dynamic comparator; the dynamic comparator, a digital logic circuit and a decoder are connected sequentially; the output end of the decoder is connected with the capacitor switches in the two DAC capacitor arrays. The DAC can reduce the building difficulty and power consumption of the Delta-Sigma ADC configuration.

Description

technical field [0001] The invention relates to the technical field of communication baseband signal processing, in particular to a successive approximation digital-to-analog converter with feedback in advance and a corresponding Delta-Sigma ADC architecture. Background technique [0002] In 1975, Professor P.R.Gary of the University of California, Berkeley proposed a SAR ADC structure based on charge distribution. The DAC (Digital-to-Analog Converter) type that is really suitable for SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is capacitive, because It not only has good matching effect, but also has no static power consumption. At the same time, the capacitor array can also be used as a sampling and holding capacitor, so that there is no need to design another sampling capacitor, thereby saving area. After years of research, SAR ADC has developed rapidly, which is mainly due to the extremely low power consumption, medium precision and speed of t...

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Problems solved by technology

[0003] In 2006, S.W.Chen proposed a SAR ADC structure based on asynchronous logic. In the synchronous logic, the same time should be allocated to each bit, which would lead to excess conversion time for the LSBs (low bits), which would affect the conversion rate.

[0006] In recent years, a variety of other structures can be obtained through the combination of different types of ADCs, which can enable ADCs to achieve better performance, such as the combination of SAR and Pipeline, which can achieve the purpose of low power consumption at higher rates; Delta- The combination of Sigma and SAR can achieve the purpose of lower power consumption under high precision. However, the current schemes have not fully utilized the advantages of SAR's low power consumption. Therefore, it is necessary to conduct in-depth research to further reduce power consumption.

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