29 results about "Clock transition" patented technology

The invention discloses a multi-photon phase detection method, device and system based on closed-loop quantum coherence and clock transition, and aims to solve the problems that the working frequency of an existing atom sensor is limited and the existing atom sensor is easily interfered by amplitude noise. According to the method, a closed ring is constructed in an atomic medium by applying a light field, a working alternating-current magnetic field and an auxiliary alternating-current magnetic field. The sum of the working frequency and the auxiliary frequency is set to be equal to the transition frequency of the first-order magnetic insensitive clock of the atom, so that decoupling of the working frequency to be measured and the inherent frequency of the atom is realized, and continuous tuning can be performed in a broadband range from Hertz to gigahertz. To-be-measured phase information is carried in a global phase of a closed loop, and is extracted by measuring an optical response signal and performing synchronous demodulation. According to the scheme, the self-consistency of the closed loop phase and the stability of clock transition are utilized, the influence of driving field amplitude noise and environment magnetic field fluctuation is effectively restrained, and the method is suitable for the fields of high-precision electromagnetic detection, broadband communication and the like.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

In an embodiment, a latch device includes a functional clock input node configured to receive a functional clock signal that periodically transitions between an active phase and an inactive phase; and a latch circuit comprising a plurality of gates, the latch circuit configured to latch a data value at an input node based on the functional clock signal being in the active phase; and output the data value at an output node until a different data value is received at the data input node; wherein the plurality of gates includes a plurality of clocked gates and a plurality of non-clocked gates, the plurality of clocked gates including a maximum of three clocked gates; and wherein the latch circuit preserves a static state in the plurality of non-clocked gates across clock transitions as long as the data value at the data input node matches the latched data value.

The present invention discloses a highly charged Nickel ion optical clock and its implementation method. It uses Ni12+ ions as the clock's reference system, which provides superior anti-interference capabilities and measurement precision compared to conventional low-charge-state ion optical clocks. The Ni12+ ions possess two transition spectral lines at 498 nm and 511 nm that can serve as clock transitions. Utilizing both 498 nm and 511 nm lasers enables a single ion reference system to output two clock signals, allowing for mutual verification. Frequency calibration using these two laser frequencies facilitates the timely detection of operational issues through abrupt changes in their frequency ratio. This approach avoids the problem inherent in a single optical frequency clock, where losing synchronization with the time reference can result in immediately undetectable, erroneous clock signal outputs, thereby significantly enhancing the overall stability of the optical clock.

The invention belongs to the technical field of integrated circuits, and particularly relates to an 8: 1 high-speed parallel-to-serial circuit which comprises a pulse generation circuit unit, a buffer circuit unit, a data sampling circuit unit and a summing circuit unit. According to the circuit, an eight-phase clock is converted into eight paths of pulse signals with the duty ratio of 1 / 8 through a pulse generation circuit unit, sequential sampling of eight paths of parallel data in one clock period is achieved in cooperation with a pre-charging-sampling-resetting stage working mode, and the serial output rate is increased to be eight times of the input clock frequency; meanwhile, the summing circuit adopts gradual merging logic of selecting one from two and one from four, so that the problem of sharp increase of load capacitance of an output node caused by direct one from eight is avoided, the charging and discharging time of the circuit is greatly shortened, and the working speed of the circuit and the data transmission accuracy in a high-speed scene are improved. The problems that the performance of an existing circuit is limited due to load imbalance, and the maximum data rate of a parallel-to-serial circuit is limited by an input clock are solved.

The invention relates to the technical field of optical clock metering instruments, in particular to a microscopic particle mass measurement method and system based on an optical lattice clock, and the method comprises the steps: forming a one-dimensional horizontal shallow light lattice to constrain a to-be-measured microscopic particle based on an optical lattice clock platform; firstly, to-be-measured particles are subjected to laser cooling and then loaded to optical lattices, and the to-be-measured particles are prepared to a ground state single Zeeman sub-energy level through optical pumping. Then, modulating a beam of lattice light in the one-dimensional horizontal shallow light lattice to enable the lattice light to periodically shake; then, determining the line widths of clock transition spectral lines of the particles to be measured under different modulation amplitudes, and finding out the critical modulation amplitude corresponding to the minimum line width; and finally, according to the critical modulation amplitude and the lattice light wavelength, accurately deducing the absolute mass of the microscopic particles imprisoned by the light lattice.

This invention relates to a method and system for implementing a DSMC communication interface between an RK3576 ARM and an FPGA. The system initiates DMA transfer and specifies the data read location on the ARM side, while the FPGA initializes the input port and bidirectional data bus. The ARM side sends the read address, and the FPGA performs clock conversion, chip select signal processing, and clock counting. It detects the read operation flag and switches the bus to output mode. The DRAM module reads data and returns it to the FPGA side, and the ARM side receives the data via DMA. The FPGA side dynamically identifies the transmitted data length and ensures clock synchronization to complete the data transmission. This invention solves the problems of high DSMC bus protocol overhead and low transmission bandwidth. By optimizing clock management and data transmission processes, it significantly improves bus bandwidth utilization, reduces transmission latency, and enhances system flexibility and data transmission efficiency, making it suitable for high-speed data transmission scenarios.

The application provides a fault detection method and device, which is applied to a BIT unit of a servo system of an optoelectronic device, the BIT unit is arranged in a direct connection manner between a motion controller and a position sensor, a first clock signal output by the motion controller is opposite in polarity to a second clock signal of a BISS-C protocol adopted by the position sensor, and the method comprises the following steps: in response to a detection signal instruction, performing BIT period detection on the first clock signal; performing conversion processing on the first clock signal of the current period to obtain a first clock conversion signal, the first clock conversion signal is the same in polarity as the second clock signal; judging whether the first clock conversion signal is high when idle; if the first clock conversion signal is high, it is determined that the working state of the position sensor is a normal state and the working state of the motion controller is a fault state; if the first clock conversion signal is low, it is determined that the working state of the position sensor is a fault state. It can be seen that the application can accurately locate the fault point and effectively solve the problem of high I / O resource occupation.

A signal encoding and decoding protocol to transmit both clock information and a data payload in a single line is disclosed. Data may be encoded in a unipolar non-return-to-zero line in which an initial pulse width determines a clock frequency, followed by a series of pulses indicating the data payload. Each clock transition following an initial synchronization pulse indicates a data bit in which the value of the bit is determined in relation to the previous bit. Edge information may indicate a change in bit value from the previous bit. If the transmission signal remains at the same level for a subsequent clock period, the bit value remains the same.

The invention particularly relates to a method for improving the frequency measurement accuracy of an optical lattice clock in a microgravity environment, which comprises the following steps of: splitting two beams of lattice light through a lattice light laser, respectively splitting two beams of lattice light from each beam of lattice light, and forming two one-dimensional horizontal optical lattices by four beams of lattice light; wherein a certain distance exists between the beam waist positions of the two one-dimensional horizontal optical lattices in the vertical direction, the midpoint position of the two one-dimensional horizontal optical lattices is the position of a magnetic field zero point in the magneto-optical trap, the projections of the axial directions of the two horizontal optical lattices in the vertical plane are parallel to each other, and the projections of the axial directions of the two horizontal optical lattices in the horizontal plane are perpendicular to each other; an acousto-optic modulator with identical parameters is loaded on a light path of each beam of lattice light and is used for linear frequency shift and modulation of lattice light frequency; two beams of clock laser are split by a clock laser light source to respectively excite different atomic groups in two one-dimensional horizontal optical lattices. Differential comparison of transition frequencies of different atomic group clocks is realized by synchronously detecting transition spectrum lines of different atomic group clocks, so that common-mode noise in an optical clock system is suppressed. According to the method, the optical lattice clock with ultra-high frequency measurement precision in a microgravity environment can be realized.

Embodiments of the present application provide a circuit logic synthesis parameter optimization method, device, equipment and medium, the method comprises: obtaining initial clock uncertainty parameter and initial clock conversion time parameter; according to initial clock uncertainty parameter, initial clock conversion time parameter and preset optimization model, determine optimization clock uncertainty parameter and optimization clock conversion time parameter;According to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine timing score and area score;In the case where timing score and area score meet the preset score condition, according to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine target clock uncertainty parameter and target clock conversion time parameter;In this way, the optimized clock uncertainty parameter and clock conversion time parameter can be accurately calculated.The problem of parameter setting depending on experience and lacking scientificity is solved, and the accuracy and reliability of clock tree design are improved.

The application discloses a kind of based on FPGA's multi-protocol routing cross device and method, belong to communication technical field, the device includes: adaptive input identification locking unit respectively receives the data of different protocol type, data is adapted to frequency by dynamic switching state machine, pass through protocol locking mark identification to identify specific frame and distribute data type code;High-speed clock domain transition unit writes data and data type code in FIFO, when reaching half full, data is read using high-speed clock and adds valid mark;Cross configuration unit according to configuration information, data and valid mark and data type code are crossed;Adaptive output unit carries out output end SERDES frequency configuration, the phase of SERDES output clock is adjusted based on digital phase-locked loop using valid mark and high-speed clock, constructs sending clock, and data is output on sending clock from high-speed clock transition.The application realizes the routing cross function of multi-protocol with less FPGA logic resource and more optimal timing.

This application provides a continuous cold atom optical clock based on optical clusters, relating to the fields of cold atom technology and atomic clocks. It includes a first laser, a second laser, a first acousto-optic modulator, a second acousto-optic modulator, a third acousto-optic modulator, a first polarizer, a first polarizing beam splitter, a vacuum chamber, an electro-optic modulator, a detector, and a servo feedback circuit. By combining cold atom optical cluster technology with an atomic clock, a cold atom optical clock based on cold atom optical clusters is constructed. By maintaining the continuous action of the probe light, while the atoms are continuously cooled, the probe light can continuously act on the cold atom optical clusters, thereby obtaining continuous and stable clock transition spectra, realizing a continuous optical clock based on cold atom optical clusters, and obtaining continuous atomic clock transition signals. Furthermore, the probe light used to detect the atomic clock transition spectra and the re-pump light used to cool the atoms are provided by the same laser, which simplifies the optical clock structure.

A clock conversion circuit is disclosed that includes a first switch connected between a first input node for receiving a second input clock and a first node and operative in response to a first logic state of the first input clock, the second input clock delayed by up to 90 degrees with respect to the first input clock; a second switch connected between a second input node for receiving the first input clock and a second node and operative in response to a second logic state of the second input clock; and a third switch connected between the second node and a ground node and operative in response to a first logic state of the second input clock opposite the second logic state of the second input clock.

A reference clock switching controller for a PLL including select circuitry and a reset controller. The PLL includes a phase detector receiving a feedback clock and a selected reference clock, and a frequency divider receiving an output clock and providing the feedback clock. The select circuitry selects from among multiple reference clocks based on a select signal to provide the selected reference clock. The reset controller resets the phase detector in response to a transition of the select signal and releases the phase detector upon a following falling edge of the selected reference clock. The reset controller resets the frequency divider in response to the transition of the select signal and releases the frequency divider after the phase detector is released from reset upon a following rising edge of the selected reference clock. A phase limit controller limits phase error during clock switching by minimizing delay of feedback clock transitions.

An electronic state splitter for atoms comprises an atom supplier, an atom movement path, a probe laser source, and a magnetic field generator. The atom supplier supplies atoms moving at a constant velocity along the atom movement path. The probe laser source supplies a probe laser propagating in the atom movement path in the same direction as or opposite to the motion of the atoms on the same axis as the atom movement path. The magnetic field generator generates a magnetic field orthogonal to the atom movement path in the atom movement path to mix the wave function of the clock upper state with the electronic state allowing electric dipole transitions, allowing pulsed excitation of clock transitions by the probe laser uniform in time and space. Accordingly, continuous spectroscopy of atomic transitions and frequency control of the probe laser are possible, which improves the stability of the atomic clock.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

In many embodiments of the invention, a tap delay line phase detector circuit includes a delay chain including a plurality of delay cells connected in series, each delay cell configured to introduce a predetermined time delay to a reference clock signal, a plurality of registers positioned at tap points along the delay chain, each register configured to sample a delayed version of the reference clock signal after a successive delay cell, a high-speed clock configured to provide timing signals to the plurality of registers, and a plurality of edge detectors configured to analyze outputs from the plurality of registers to determine clock transition timing, wherein the plurality of edge detectors generate edge detection signals that indicate timing relationships between the reference clock signal and the high-speed clock.

The application relates to the technical field of electronic design automation, and discloses a gated clock conversion method and device, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring the logical relationship of an original clock signal, a clock control signal and a gated clock signal of a timing device; solving whether the gated clock signal and the original clock signal satisfy a preset constant condition through a Boolean satisfiability problem; if yes, determining a clock domination constant and a clock controlled constant; determining an enable control signal based on the clock domination constant, the clock controlled constant, the clock control signal and the logical relationship, and determining an updated clock signal based on the clock domination constant, the clock controlled constant and the original clock signal; and driving the timing device based on the enable control signal and the updated clock signal, so as to realize conversion of the gated clock signal. The application can automatically identify and convert the gated clock composed of various combination logics, and has the technical effects of improving conversion success rate and design efficiency.

In many embodiments of the invention, a tap delay line phase detector circuit includes a delay chain including a plurality of delay cells connected in series, each delay cell configured to introduce a predetermined time delay to a reference clock signal, a plurality of registers positioned at tap points along the delay chain, each register configured to sample a delayed version of the reference clock signal after a successive delay cell, a high-speed clock configured to provide timing signals to the plurality of registers, and a plurality of edge detectors configured to analyze outputs from the plurality of registers to determine clock transition timing, wherein the plurality of edge detectors generate edge detection signals that indicate timing relationships between the reference clock signal and the high-speed clock.

Aspects of the disclosure are directed to a dynamic master slave flip flop circuit. In accordance with one aspect, the disclosure includes a master latch section configured to receive an input signal asserted at a HIGH state of the input signal; a clock circuit coupled to the master latch section, the clock circuit configured to execute a positive clock transition of a clock signal; and a slave latch section coupled to the master latch section and the clock circuit, the slave latch section configured to transition a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition.

This application relates to a clock transmission method, a magnetic resonance imaging system, and an apparatus for a magnetic resonance imaging (MRI) system. The method includes: converting a clock signal through a transmitting circuit to obtain a differential clock; converting the differential clock into an optical signal using the transmitting fiber optic device and transmitting it to a receiving fiber optic device; converting the optical signal into an electrical signal using the receiving fiber optic device and transmitting it to the receiving circuit; and converting the electrical signal into a single-channel clock and filtering it to obtain the clock signal. This application transmits the clock signal via optical fiber, which can achieve clock synchronization between the transmitting and receiving ends of the MRI system, ensuring phase coherence. Furthermore, optical fiber transmission exhibits low signal attenuation and enables long-distance transmission, ultimately effectively improving the stability and quality of the clock signal in the MRI system and contributing to improved imaging quality.

The atomic electronic state separator (1) of the present invention includes: an atomic supply unit (11), an atomic movement path (12), a probe laser source (13), and a magnetic field generating unit (M). The atomic supply unit (11) supplies atoms that move in the atomic movement path (12) at a certain speed. The probe laser source (13) supplies a probe laser that propagates coaxially with the atomic movement path (12) in a direction opposite to or the same as the direction of atomic movement. The magnetic field generating unit (M) generates a magnetic field orthogonal to the atomic movement path (12) in the atomic movement path (12) and mixes it with the wave function of the electronic state that allows electric dipole transitions, thereby enabling pulse excitation of clock transitions based on the same probe laser in time and space. Alternatively, a magnetic shielding member can pulse excite clock transitions by shielding the magnetic field applied in the atomic movement path (12) and spatially changing the Zeeman frequency shift, thereby enabling pulse excitation of clock transitions by the same probe laser in time and space. As a result, it is possible to continuously perform spectral analysis of atomic transitions and frequency control of the detection laser, thereby improving the stability of the atomic clock.

The application relates to a method for improving the frequency measurement precision of an optical lattice clock in a microgravity environment, which comprises the following steps: two beams of lattice light are divided from one lattice light laser, each beam of lattice light is further divided into two beams of lattice light, and four beams of lattice light form two one-dimensional horizontal optical lattices; wherein the waist positions of the two one-dimensional horizontal optical lattices have a certain interval in the vertical direction, and the midpoint position is the position of the magnetic field zero point in the magneto-optical trap; the projections of the axial directions of the two horizontal optical lattices in the vertical plane are parallel to each other, and the projections in the horizontal plane are perpendicular to each other; an acousto-optic modulator with the same parameters is loaded on the light path of each beam of lattice light, and is used for linear frequency shift and modulation of the lattice light frequency; two clock laser beams are divided from one clock laser source, and are used for exciting different atomic groups in the two one-dimensional horizontal optical lattices. By synchronously detecting the clock transition spectral lines of each different atomic group, the differential comparison of the clock transition frequencies of different atomic groups is realized, so that the common-mode noise in the optical clock system is suppressed. The method can realize an optical lattice clock with super-high frequency measurement precision in a microgravity environment.

A spectroscopic device 1 comprises: a first atomic movement path 11 that is provided with an atom supply unit 10; a second atomic movement path 12 that, at a finite angle, intersects the first atomic movement path 11 at a first intersection position P1; a third atomic movement path 13 that, at a finite angle, intersects the second atomic movement path 12 at a second intersection position P2; and a clock laser light source 20 that supplies a clock laser L20 which propagates in a direction opposite to or the same as that of the movement of atoms on the second atomic movement path 12. A spectroscopic region SP where the clock laser L20 causes excitation of clock transition in atoms is formed between the first intersection position P1 and the second intersection position P2 on the second atomic movement path 12.

The object of this invention is to realize a new magnetic field correction coil that can also be miniaturized or portable in terms of physical packaging. The 3-axis magnetic field correction coil (96) has a first coil group and a second coil group in the X-axis direction passing through the clock transition space where atoms are arranged. The first coil group is a Helmholtz type coil, which is formed in a point-symmetric shape centered on the clock transition space (52). The second coil group is a non-Helmholtz type coil, which is formed in the X-axis direction in a point-symmetric shape centered on the clock transition space (52), and the coil size, coil shape or inter-coil spacing is different from that of the first coil group.

A signal encoding and decoding protocol to transmit both clock information and a data payload in a single line is disclosed. Data may be encoded in a unipolar non-return-to-zero line in which an initial pulse width determines a clock frequency, followed by a series of pulses indicating the data payload. Each clock transition following an initial synchronization pulse indicates a data bit in which the value of the bit is determined in relation to the previous bit. Edge information may indicate a change in bit value from the previous bit. If the transmission signal remains at the same level for a subsequent clock period, the bit value remains the same.

This invention discloses a cold atom two-photon transition physics device based on diffuse reflection cooling, comprising a glass chamber, a diffuse reflection coating, an optical unit, and a detection unit. The glass chamber is an ultra-high vacuum cavity sealed and connected to an external ultra-high vacuum system and an atomic source. Its outer wall is covered with a diffuse reflection coating, on which are formed apertures for cooling light, re-pumping light, excitation light, and fluorescence output. The optical unit includes cooling light, re-pumping light, and excitation light. The cooling light and re-pumping light form a global diffuse reflection cooling light field through the diffuse reflection coating, preparing three-dimensionally distributed cold atom clusters within the cavity. The excitation light passes through the cavity and is reflected back to form a bidirectional opposing light path, constituting a two-photon transition excitation light field. The detection unit collects, filters, and converges the fluorescence signal before outputting it through a photodetector. This invention features a simple structure, small size, and low power consumption, and can output clock transition spectra with high signal-to-noise ratio and narrow linewidth, providing a novel technical solution for small-scale, high-precision optical frequency standards.

Aspects of the disclosure are directed to a dynamic master slave flip flop circuit. In accordance with one aspect, the disclosure includes a master latch section configured to receive an input signal asserted at a HIGH state of the input signal; a clock circuit coupled to the master latch section, the clock circuit configured to execute a positive clock transition of a clock signal; and a slave latch section coupled to the master latch section and the clock circuit, the slave latch section configured to transition a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition.