120 results about "Clock transition" patented technology

A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.

A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit. Also, the circuit, system, and method support double data rate (DDR) data and echo clock generation, where the echo clock transitions in sync with the DDR output.

Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

The present invention is directed to a method and apparatus for simulating digital electronic systems. The signal integrity of a digital electronic system is assessed by analyzing traces (e.g. wires between components) for cross coupling. Problem areas are identified by monitoring storage components or output ports of the electronic system. Wires (traces), which carry signal transitions to the storage component or output ports are analyzed and quantified based on timing windows associated with the wires (traces). The clock transitions into a storage device are analyzed and vulnerability windows are identified for the storage device. The vulnerability windows are time periods when cross coupling may occur on a storage device. If a timing window overlaps a vulnerability window the timing window is considered a critical timing window. Devices driving the transition on wires with critical timing windows are then analyzed. Adjustments are made to the parameters of the driving devices to create a worse case scenario. The worse case scenario is simulated and analyzed for cross-coupling.

The invention discloses an optical pumping rubidium atomic clock based on modulation transfer spectrum frequency stabilization laser, and a preparation method thereof. The optical pumping rubidium atomic clock comprises a narrow linewidth laser, a beam expander, a half wave plate, a polarization beam splitting prism, a phase modulator, a rubidium atomic bubble for laser frequency stabilization, ahigh-speed photoelectric detector, a mixer, a high-speed servo feedback circuit, a radio frequency signal source, a laser driving power supply, a convex lens, an acoustic optical modulator, a rubidiumatomic bubble for obtaining a clock transition spectral line, a crystal oscillator frequency synthesizer and a control circuit part; the radio frequency signal source generates a modulation signal, the modulation signal is input into the phase modulator to perform phase modulation on pumping laser, meanwhile, a demodulation signal is generated to perform mixing demodulation with the signal from the photoelectric detector to obtain an error signal, and the laser driving power supply is controlled by the high-speed servo feedback circuit to realize high-stability narrow linewidth laser based ona modulation transfer spectrum. The laser subjected to frequency stabilization is used as the pumping laser of the optical pumping rubidium atomic clock to obtain a high-performance optical pumping rubidium atomic clock.

The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.

An arrangement for clock control in a device receiving a clock from an external source includes switching means (101) for switching an external clock through to the device as an internal clock, and clock request generation means (102, 103), adapted to switch clock signal through to the external clock controller as requests for suppressing and restarting the external clock. Control means (104) are provided in the form of a state machine to control the generation of the internal clock through the switching means, and to control the clock request generation means in accordance with a predetermined state of two signals, one generated internally by the device, the other by the external clock controller (20). The clock request generation means are also coupled to a clock start module adapted to receive several input signals (12) for signalling an event requiring the clocked operation of the device.

A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

A low voltage differential signal receiving device includes two differential receivers, two oversamplers, a phase locked loop, and a clock edge and data boundary detection & data extraction logic module. Clock and data signals are transmitted via channels having the same circuit layout, so that the clock signal is treated as another type of data signal. A frequency of sampling input clock and data is increased via asynchronous clock, clock transition is detected, and data bytes are extracted from clock and data samples. Therefore, the clock signal and the data signal have the same delay time to avoid any sampling error due to a difference in time sequence between the clock and the data. Meanwhile, due to the accurately increased sampling frequency, the sampled clock and the data signals are not adversely affected by different factors to enable upgraded data transmission efficiency and quality at the same time.

Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.

A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to operate in the fast clock domain in conjunction with hardware that performs certain device operations that is clocked by a slow clock that is always on to operate in a slow clock domain. Writing data from the processor to the hardware involves determining if a bit is to be written to a register of the slow clock domain in synchrony with a transition of the slow clock, stopping the fast clock to pause operation of the processor, writing the bit to the register of the slow clock domain upon a succeeding slow clock transition, and starting the fast clock to resume operation of the processor.

A digital-to-analog converter is disclosed, comprising an input/output circuit, a bistable circuit connected with the input/output circuit, a clock circuit connected with the input/output circuit and the bistable circuit, and a current generator circuit connected with the clock circuit. The clock circuit acts as a switch, providing current from the current generator either to the input/output circuit or to the bistable circuit. The digital input signal switches when the current generator provides current to the bistable circuit, and switching of the input signal is asserted at the output of the converter when the current generator provides current to the input/output circuit. Therefore, switching of a clock circuit signal, rather than switching of the digital input signal determines switching of the output signal, in order to reduce intersymbol interference of the converter associated with thermal hysteresis of some of the components of the converter.

A display system has a first resolution video buffer 20, and can insert a second resolution analog video signal, the first resolution being higher than the second resolution. It can sample the second resolution video signal and insert it 50 without substantially reducing the resolution of the image. An advantage over software solution is more independence from software standards. The sampling can involve asynchronous over-sampling 130 to two or more states, adequate for recreating text or attributes. Then a re-sampler 52 uses a pixel clock derived 54 by counting coincidences of image and clock transitions, and adjusting a clock phase or frequency to minimize the count.

An atomic clock at optical frequency based on atomic beam and a method for generating the atomic clock comprises: The atomic beam (8) is ejected from a pile mouth after heating an atomic pile (1) in a vacuum chamber (2); A laser (4) corresponding to frequency of a clock transition transfers the atomic beam (8) from a ground state of the clock transition to an excited state of the clock transition in a adiabatic passing mode; After interaction with the laser corresponding to the frequency of a clock transition, the atomic beam (8) passes a signal detection region with a detection laser (5), and after the interaction with the detection laser (5), each of the atoms gives off a photon of spontaneous emission; An emitted fluorescence photon signal from atoms which is excited by the detection laser (5) is explored; A clock laser (4) for exploring transition frequency of an atomic clock is modulated. The signal which is detected performs frequency locking for the frequency of the clock laser which is locked on the clock transition spectrum of the atoms so as to implement the atomic clock.

A voltage controlled oscillating means in a clock converter outputs a positive feedback signal for a positive feedback loop from one output terminal of buffer means forming a portion of a positive feedback loop using voltage controlled phase shifting means and outputs a PLL feedback signal from the other output terminal of the buffer means. The PLL feedback signal is fed back to phase detector means through a signal transmitting circuit. As a result, it is possible to form a PLL feedback loop, which is not affected by the load to thus output a stable clock signal of high frequency. Furthermore, it is possible to realize a small clock converter by narrowing the line width of a wiring pattern in the signal transmitting circuit.