Event driven dynamic logic for reducing power consumption

Abstract

Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and / or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Application Serial No. 60 / 408,407, filed September 3,2002. [0003] Statement Regarding Federally Sponsored Research or Development [0004] none [0005] Incorporation by reference of material presented on CD-ROM [0006] none technical field [0007] This invention pertains generally to digital logic circuits, and more specifically to reducing power consumption using event-driven logic where clock signals are only propagated within the circuit after true logic operations have been performed. Background technique [0008] Conventional logic circuits often utilize clock signals received through various levels of strobing within the circuit to synchronize state changes within the circuit to eliminate race conditions and other similar problems. As a result, a clock signal is applied to many gates within each logic block or logic section. For each gate that undergoes...

AI Technical Summary

Problems solved by technology

[0024] Both combinational and sequential logic circuits have been shown to similarly experience capacitive loading of clock signals, where circuit power is consumed even when no net (productive) circuit activity is occurring

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