Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL)

Abstract

A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.

Description

FIELD OF THE INVENTION[0001]This invention relates to clock buffers, and more particularly to zero-delay phase-locked loop (PLL) clock buffers.BACKGROUND OF THE INVENTION[0002]Large digital electronic systems have many blocks of circuits that must communicate with each other. Communication is facilitated by the use of clocks that synchronize data transfers. Large systems may require many clock signals that are applied to large loads. These clocks are often synchronized to each other during clock generation. Higher operating speeds required that these clocks be accurate and precise.[0003]Phase-locked loops (PLL's) are used to receive an external clock and to clean up any jitter or other signal distortions. In a PLL, an input clock is compared to a feedback clock that is generated by the PLL, and the feedback clock is altered by the PLL to match the input clock in phase and frequency.[0004]One kind of clock generator that uses a PLL is known as a zero-delay buffer. Many clocks are gen...

AI Technical Summary

Benefits of technology

The patent text describes a problem with generating clock signals in electronic systems. Clock signals are used to synchronize data transfer between circuits, but they can be affected by interference and voltage fluctuations. This can cause the clock signals to become less accurate and precise. The inventors have developed circuits to compensate for this problem and ensure the clock signals are generated with a zero-delay and are not affected by common-mode drift. This improvement can be used in differential clock generators to ensure accurate and reliable synchronization of data transfer between circuits.

Problems solved by technology

Large systems may require many clock signals that are applied to large loads.

However, today's modern systems operate at blazingly fast speeds, and the single-ended clocks have too many signal distortions that can disrupt system operation.

Any external interference tends to couple in equally to both physical wires of a differential clock, so the interference tends to cancel out.

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