Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof

a clock signal and data input technology, applied in the field of data inputprocessing methods, can solve the problems of jitter in the dlls and complicate high frequency operations, and achieve the effect of reducing the restriction of high frequency operations and maximizing the timing margin of the clock conversion par

Inactive Publication Date: 2006-05-02
SAMSUNG ELECTRONICS CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0035]According to a structure of the aforementioned unit and method, a plurality of clock signals are directly applied only to a signal-receiving clock conversion part and a clock signal output from the DLL being applied to the rema

Problems solved by technology

In other words, jitter in the DLLs c

Method used

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  • Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof
  • Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof
  • Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof

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second embodiment

[0067]FIG. 11 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL in accordance with the present invention. As shown in FIG.11, the data input-processing unit includes a clock signal-receiving synchronous circuit R_DLL 230 which generates a signal-receiving internal clock ICLK as an output clocking signal. By phase-delaying the second clock signal CLK by a predetermined time; a data input part 216 inputs data in sequential response to the first clocking signal DS that is applied simultaneously with the application of the data and to the second clocking signal CLK that is applied at a timing different from that of the first clock signal DS. An input-processing part 218 processes the data output from the data input part 216 in response to the signal-receiving internal clock ICLK of the clock signal-receiving synchronous circuit (clock signal receiving locked loop) R_DLL 230.

[0068]The structure of FIG. 11 preferably includes only a clock signal-rec...

third embodiment

[0069]FIG. 12 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL according to the present invention. The structure includes only DS_DLL 220 rather than the R_DLL 230 and DS_DLL 220 combination of the preferred embodiment. As in the other embodiments, the clocking signal bypasses the DS_DLL 220, and externally received data strobe signal DS is directly applied to the signal-receiving clock conversion part CCP through a buffer 223.

[0070]FIGS. 13 and 14 illustrate representative DLLs, such as R_DLL 230 and DS_DLL 220 shown in FIGS. 9, 11 and 12. As shown in FIG. 13, a DLL (i.e., 220, 230) may include: a signal-receiving buffer 211, which receives an input clock signal IN; a variable delay unit 213, which outputs an output clock signal OUT by delaying a signal-receiving clock signal RCLK output from the signal-receiving buffer 211 in response to an applied digital control data CON; a phase detector 215, which detects a difference in the phase betwe...

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Abstract

A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a data input-processing method applicable to a data input-processing unit, such as a microprocessor or synchronous semiconductor memory device. More particularly, the present invention relates to a multi-clock domain data input-processing unit having a clock signal receiving locked loop (a clock signal receiving synchronous circuit) and the related clock signal applying method.[0003]2. Description of the Related Art[0004]As the operational speed of a central processing unit (CPU) for controlling the operations of a computer system increases, a synchronous dynamic random access memory (hereinafter referred to as SDRAM) that operates synchronously with an external clock is widely used. Specifically, a device known as 2 bit pre-fetch type SDRAM is typically used, since the device can write and read 2 bit data simultaneously. In case of the 2 bit pre-fetch type SDRAM, it is necessary to prov...

Claims

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Application Information

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IPC IPC(8): G11C8/00G06F5/06G11C11/4096G11C7/10H03L7/081H04L7/00H04L7/02
CPCG06F5/06G11C7/1072G11C7/222H04L7/0037H04L7/02H03L7/0814H04L7/0008H04L7/0045H03L7/0816H03L7/0818G11C11/4096
Inventor CHUNG, DAE-HYUN
Owner SAMSUNG ELECTRONICS CO LTD
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