130results about How to "Fast programming" patented technology

The invention relates to an industrial robot motion planning and performance testing system and an implementation method thereof. The system comprises a database module, a man-machine interaction module, a spray gun track planning module, an analysis and display module, a robot job instruction generation module and a communication and interface module, wherein the database module realizes storage of the spray gun track and the joint variable of the spraying robot as well as the spraying tasks; the man-machine interaction module realizes parameter input and control on other modules; the spray gun track planning module is used for planning a spray gun track for optimizing the spraying effect and working out the joint variable corresponding to the track on the premise of meeting all the limits; the analysis and display module simulates and analyzes the spraying process of the spraying robot; the robot job instruction generation module realizes the function of generating spraying robot job files; and the communication and interface module is used for importing spraying task data, and uploading and downloading job files. The invention has the advantages of high programming speed, high accuracy, complete functions and strong versatility, and can be used for scientific research in various types of robots and control on the actual spraying operating system.

A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition.The material is crystallized into the conductive state and does not require electroforming.

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.

The invention discloses an automatic numerical control machining code generating system, which comprises an input module, an analysis module, a database, an output module, a display module and a correction module, wherein the input module is connected with the analysis module, the analysis module is connected with the output module, and the output module is respectively connected with the database, the display module, the correction module and a numerical control system; and the display module is connected with the correction module. Firstly, submodules in the input module are manually selected according to parts to be machined, parameters are input into the selected submodules and then the input parameters are transmitted to corresponding algorithm modules in the analysis module; and theanalysis module selects the corresponding algorithm modules according to the received parameters and conducts analysis to generate numerical control codes which are transmitted to the numerical control system through the output module. Since standard numerical control code frames which are preset in the algorithm modules in the analysis module are necessary for the numerical control system, the format of the automatically generated numerical control codes is consistent with the numerical control system.

An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

The design method capable of using external synchronous for a camera with various data output formats, relating to data output of the camera. A transformation between an external synchronizing signal and a CCD (charge coupled device) time sequence is carried out by utilizing a programmable gate array module, so as to realize two-way communication with the external synchronization. A synchronizing signal is transmitted by externally connecting an input line module, an input field module, an input clock module and an input exposure module on FPGA (filed programmable gate array), and the two-way communication with the external synchronization is realized by externally connecting a circumscribed high-speed serial interface, a parallel interface, a low-voltage differential signal interface and a network interface. Software control FPGA uses an external control signal firstly. The control signal can be one or two or three or four of an input field synchronizing signal, an input line synchronizing signal, an input clock signal and an input exposure control signal. The external device can be added with a video compression chip, or an embedded chip, or both the video compression chip and the embedded chip. The invention enables the exposure time to be synchronous with a specific event, and to be synchronous with an operation processing of the external device, enables the software to program fast, and enables program running time and memory using to be less.

A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second capacitive element, the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node that can be connected to an element for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.

A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between two supply terminals, each branch including at least one transistor of a first type and one transistor of a second type, the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal, the respective drains of the transistors of the first type being connected to the respective inputs of a comparator whose output provides an indication of the residual voltage in the charge retention element.

The invention discloses an OLED data driving circuit, an active TFT OLED panel based on the OLED data driving circuit and a driving method of the active TFT OLED panel based on the OLED data driving circuit. The current driving circuit is formed by the following parts including the current feed-forward part, the current feedback part, the comparison amplifier, the dynamic compensation part and the polarization power source. By means of the data driving circuit, current type TFT OLED pixels can be rapidly programmed with high accuracy. A gate driving line of the active TFT OLED panel based on the data driving circuit is two times that of a common panel, pixels in the direction of one gate driving line are divided into two different groups according to the parity of a dateline where the pixels are located, gate scanning time of two sets of pixels in the direction of the same line is respectively a half of the gate scanning time of the common panel, and two gate scanning lines are complemented and sequentially open the pixels in the direction of the same line.

A vehicular programmable transceiver includes a digital radio frequency memory (DRFM) having at least one register configured to sample and hold a radio frequency input signal in response to a clock signal and to generate an output signal having a carrier frequency generated in response to the sampled and held input signal.

The embodiment of the invention provides a task processing flow arrangement method and device and electronic equipment. The method comprises the following steps: determining service nodes according toa target task, establishing a flow relationship between the service nodes during service processing according to an execution sequence of the service nodes in the target task, and configuring at least one node processing task for each service node; triggering conditions are set for all the service nodes according to a preset triggering mode of the service nodes, wherein when any service node meets the triggering conditions, a node processing task configured for the service node is executed; and arranging a process for processing the target task based on the service node, the process relationship of the service node, the node processing task corresponding to the service node and the triggering condition. The technical scheme can be applied to the field of supervision, and arrangement of supervision disclosure task processing flows is realized.