Jitter tolerance testing method and circuit for high-speed serial IO interface based on BIST

Abstract

The invention discloses a jitter tolerance testing method and circuit for a high-speed serial IO interface based on BIST (built-in self-test). The circuit mainly consists of a CDR circuit module, a jitter injection module, and an error code detection module. A CDR circuit at the receiving end of the high-speed serial IO interface is additionally provided with the jitter injection module and the error code detection module, and can achieve the self-testing of the jitter tolerance of the receiving end. The jitter injection module comprises a Jitter Memory, a PI (phase interpolator) and a PRBS (pseudorandom binary sequence) circuit, and is used for generating a test sequence containing jitter information. The error code detection module comprises a sequence detector (PRBS Checker), an XOR gate and an error code counter (Error Detection), and is used for detecting an error code and obtaining the number of error codes. The method and circuit achieve the self-testing of the jitter tolerance of the receiving end, and can achieve the different types of jitter injection, such as RJ (random jitter), PJ (periodic jitter), and DCD (duty cycle distortion). The BIST circuit is simple in implementation, effectively shortens the testing time, reduces the testing cost, can be used for various types of high-speed serial IO interface circuits, and is higher in practicality.

Description

technical field [0001] The invention discloses a high-speed serial IO interface jitter tolerance test method and circuit, specifically implementing jitter injection and error code detection inside a receiver circuit of the high-speed serial interface to complete the receiver jitter tolerance test. Background technique [0002] Input / output (I / O) has always played a key role in computer and industrial applications. In the early parallel I / O bus, the data alignment problem of the interface affects the effective communication with external devices. However, with the increase of processor speed, I / O has become the bottleneck of system-level performance, and improving I / O performance is very critical to improve system performance. In the current high-speed communication system, the serial communication technology SerDes (serializer / deserializer) originally used for optical fiber communication has become the key to the high-speed communication system due to its ability to comply ...

AI Technical Summary

Problems solved by technology

The two major problems faced by the jitter tolerance test are: ① Most of the bus standards require a BER≤10 -12 Under the jitter tolerance test, the device must send at least 10 13 A bit of data, and the jitter tolerance test needs to test multiple frequencies, which will make the test time very long; ②The jitter tolerance test needs to generate different types of jitter and mix them to produce controllable jitter close to the real ratio The composition is more complicated

These methods can inject SJ very well and perform jitter tolerance test on the circuit under test, but these methods can only inject PJ of a single frequency, which cannot simulate the actual situation well

Ahmed and Kwasniewski implemented multiple jitter injections through Digital Integrator, Adder, Delay Control Logic and Variable Vernier Delay, but the circuit implementation is complicated and not intuitive enough

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