96 results about "Power integrity" patented technology

Model-order reduction techniques are described for RLC circuits modeling the VLSI layouts. A structured model order reduction is developed to preserve the block-level sparsity, hierarchy and latency. In addition, a structured and parameterized model order reduction is developed to generate macromodels for design optimizations of VLSI layouts. The applications are thermal via allocation under the dynamic thermal integrity and via stapling to simultaneously optimize thermal and power integrity.

Embodiments relate to a sensing device configured to sense the environment of an antenna in a wireless communications or wireless power transfer device without impacting data signal or transferred power integrity. By incorporating a sensing device in the wireless device that operates outside the data signal operating and operational power transfer frequency(s) of the antenna, send/receive data signal integrity may be retained while sensing the environment of the antenna. The sensing device may further use properties of the sensed environment to adjust the configuration of a tunable antenna to decrease signal degradation due to the environment and increase battery life or power transfer efficiency of the wireless device.

A system and method is provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

The invention relates to the field of very large scale integrated (VLSI) circuit technique, especially a PI solving method for IC-package-PCB cooperative design for solving power supply integrity problem in back-end design, comprising: 1) building a circuit model suitable for VLSI PI analysis; 2) analyzing and extracting parasitical parameters corresponding to the circuit mode; 3) determining design indexes in the PI design; 4) utilizing EDA tool and owned algorithm model to make accurate simulation and calculation; 5) on the premise of considering power supply integrity, according to the PI design indexes and simulated results, quickly determining a proper number of I/Os of power supply.

A test circuit and method for measuring power supply integrity is provided. The circuit may be incorporated on-chip and is small enough to be integrated many times across the surface of the die for measuring integrity parameters at several locations on the chip. The circuit instantaneously measures, e.g., the rail voltage of a power supply, which may be fluctuating at the time of measurement. In addition, the circuit isolates itself from all chip power rails for the duration of the measurement, thereby eliminating any influence of external noise on the measurement. A storage capacitor is charged up to full power rail voltage for powering up a comparator. Then, the comparator is isolated from the power rails and the measurements are taken. Based upon the measurements, certain power supply integrity parameters are quantified including ground bounce and power droop.

The invention relates to a hybrid mesh partition method in the field of electronic technologies, in particular to the hybrid mesh partition method with the design of integrity of a system-level packaging power supply. The hybrid mesh partition method comprises the following steps: (1) decomposing an irregular power supply/ground plane into a series of convex polygons by utilizing convex partition treatment; (2) obtaining an optimal rectangular mesh based on the recursive partitioning technology of the rectangular mesh, setting auxiliary ports on sides of the rectangular mesh, and establishing the transfer impedance relationship among the ports; (3) adopting a triangular mesh to fill the remaining structure, and carrying out modeling of an equivalent circuit for the triangular mesh; (4) establishing the electrical relationship among the ports at an interface of the rectangular mesh and the triangular mesh; and (5) solving simultaneous overall equations. The hybrid mesh partition method has the advantages of a wide range of applications, few internal nodes, high analysis precision and efficiency and the like.

A broadband Green's function computation technique that employs low wavenumber extraction on a modal summation is used to model the waveguide behavior of electronic components, systems, and interconnects on a printed circuit board. Use of the broadband technique permits discretizing the surface of the printed circuit board across a wide range of frequencies all at once. The broadband Green's function is also extended to via waveguides on circuit boards and power/ground plane waveguides of arbitrary shape. Such a method can analyze a given circuit board geometry over a broad frequency range several hundred times faster than is otherwise possible with existing commercial analysis tools. The present method is useful in electronic design automation for analyzing signal integrity and power integrity, reducing electromagnetic interference and ensuring electromagnetic compatibility.

The invention discloses a capacitor-carried power supply ground plane modeling and capacitor decoupling radius simulating method. The method includes the steps of recording coordinates of an input/output port and a decoupling capacitor port, calculating port coefficients and frequency domain responses of all resonance modes according to a resonant cavity formula or based on a double-frequency-point approximation algorithm resonant cavity formula, obtaining all capacitor division schemes according to the port coefficients, the frequency domain responses of all the resonance modes, the number of the modes, the capacitor frequency domain responses and the number of capacitors, converting the divided capacitors into a power supply ground plane resonant cavity model to obtain a capacitor-carried power supply ground plane resonant cavity formula, calculating power supply ground plane actual frequency domain impedance distribution through the resonant cavity formula, and extracting the capacitor decoupling radius on the basis of the impedance distribution. By means of the method, the problem that capacitor-carried power supply ground plane modeling can not be conducted through a resonant cavity algorithm is solved, a rapid, easy and convenient method is provided for load-carried power supply ground plane modeling, and reliable guidance is provided for selection and placement of the decoupling capacitors in power supply integrity design through the decoupling radius.

The invention provides a method for constructing a small power integrity risk index of a power supply station based on big data, belonging to the data processing field. The method includes: building asmall and micro power integrity risk evaluation data center based on business information system, building small and micro power integrity risk evaluation index, based on the actual data, evaluatingthe small micro-power integrity risk indicators, extracting the actual data to evaluate and screen the indicators, determining the index weight, calculating the small micro-power integrity risk index,carrying out the small micro-power integrity risk rating, and carrying out the trend analysis and early warning of the small micro-power integrity risk index based on the actual data. By using the rich business data accumulated in existing business information systems, current data is rated by constructing an evaluation system, so corresponding measures are taken according to the rating results to improve the small power risk management and information level of power supply substation, effectively identify the small power integrity risk and enhance the risk prevention and control capacity.

The invention discloses a PDN alternating current noise analysis method of a three-dimensional integrated circuit, which is used for analyzing the magnitude of PDN alternating current noise of the three-dimensional integrated circuit. The method comprises the following implementation steps: (1) constructing three physical models; (2) obtaining respective parasitic parameter values of the three physical models; (3) calculating parasitic parameter values; (4) obtaining simulated parasitic parameter values; (5) constructing an equivalent circuit model of the power distribution network PDN; (6) setting a power distribution network PDN alternating current noise simulation environment; And (7) obtaining the maximum alternating current noise of the power distribution network PDN of the three-dimensional integrated circuit. The method can quickly and accurately analyze and obtain the magnitude of the alternating current noise of the PDN of the three-dimensional integrated circuit, and can be used for providing a basis for design analysis of the integrity of the power supply in the power distribution network of the high-speed three-dimensional integrated circuit and evaluation of the packaging reliability.

A BGA package comprises a substrate, a chip disposed on the substrate, and a plurality of solder balls disposed under the substrate. The substrate further has a plurality of ball pads and a solder mask having a plurality of openings to expose the ball pads where the ball pads include two or more non-signal pads. Solder mask further has a trench connecting the ones of the openings on the non-signal pads where the trench is filled with solder paste so that the solder balls bonded to the non-signal pads are electrically connected together to achieve power integrity and to reduce numbers of power/ground layers to make the package thinner and the substrate cost lower.

The invention provides a probe card and a printed circuit board used for the same, which are used for promoting the power integrity during testing. The printed circuit board provided by the invention is defined as a welding spot area, a routing area and an input area, wherein the welding spot area comprises a plurality of first power welding pad groups; the input area comprises a plurality of second welding pad groups corresponding to the first power welding pad groups; and each first power welding pad group is insulated from each second welding pad group. The probe card provided by the invention adopts the printed circuit board and is combined with an external wire or an external power plane to obtain the better power integrity.

The invention relates to the application field of big data, in particular to a power supply station small power clean and honest risk supervision and control system based on an enterprise cloud platform. The system comprises a data center module, a model and algorithm library module, a management module, a risk identification and early warning module, a management control module and a processing module. The data center module is connected with an enterprise cloud platform; The model and algorithm library module are connected with a data center module and a management module; The management module is connected with a data center module; The risk identification and early warning module is connected with the management module; The management and control module is connected with a risk identification and early warning module; The processing module is connected with a risk identification and early warning module and a management and control module. The invention has the beneficial effects of realizing the supervision and control of the small power incorruptibility risk of the power supply substation.

The invention discloses a power distribution network based on a plane C-type bridge electromagnetic band gap structure. The power distribution network comprises a power plane, a dielectric substrate and a ground plane, wherein the power plane, the dielectric substrate and the ground plane are sequentially arranged. The power plane comprises an electromagnetic band gap structure unit matrix. Each electromagnetic band gap structure unit is of a central symmetry structure and provided with four C-type bridges in a led mode, the four C-type bridges are connected with four adjacent electromagnetic band gap structure units respectively, and the two ends of any C-type bridge are connected to the opposite sides of two adjacent electromagnetic band gap structure units respectively. According to the power distribution network, the plane C-type bridge electromagnetic band gap structure units are periodically carved in the power plane of the power distribution network, simultaneous switching noise between the power plane and the ground plane in the power distribution network can be suppressed within a wide frequency range, and the good power integrity of a system can be obtained.