52 results about "Power integrity" patented technology

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention relates to a power supply integrity test method and device for a silicon substrate, and the method and device are applied to an upper computer in a test device connected with a to-be-tested silicon substrate, and the method comprises the steps: carrying out the failure behavior detection of the to-be-tested silicon substrate, and carrying out the detection of the failure behavior of the to-be-tested silicon substrate under the condition that the to-be-tested silicon substrate does not have the failure behavior; acquiring test data information acquired by a plurality of sensors arranged in the to-be-tested silicon substrate through a preset acquisition channel; wherein a plurality of sensors are arranged in different preset areas of the to-be-tested silicon substrate, and each sensor is used for feeding back acquired test data information of the position of the sensor to the upper computer; and determining a target area without errors in each area of the to-be-tested silicon substrate based on the test data information, and executing a reliability test on the target area to obtain an internal state test result of the to-be-tested silicon substrate. According to the invention, an accurate test result of the internal state of the silicon substrate can be obtained.

The invention discloses a direct current simulation method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining a structured data template file filled by a user, and enabling the structured data template file to define a topological structure and simulation parameters of a power network; analyzing the structured data template file, and extracting simulation configuration data; obtaining design data of the target printed circuit board; based on the simulation configuration data and the design data, topology verification and mapping are carried out, and a power supply tree is constructed; generating setting data required by direct current simulation based on the power supply tree; and calling a direct current simulation engine based on the setting data, and executing simulation calculation to obtain a simulation result. According to the embodiment of the invention, full automation of a direct current simulation process is realized through data driving, manual setting errors are thoroughly avoided, the efficiency of power supply integrity analysis is greatly improved, and the consistency from design input to verification output is ensured.

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

A capacitor assembly and a power supply system are provided. The capacitor assembly comprises: a first carrier plate and a second carrier plate, which are arranged in a stacking manner along a first direction and are spaced apart from each other, and the first carrier plate is electrically connected with the second carrier plate; a first layer of capacitors, which are arranged on a side of the first carrier plate facing the second carrier plate and are electrically connected with the first carrier plate; and a second layer of capacitors, which are arranged on a side of the second carrier plate facing away from the first carrier plate and are electrically connected with the second carrier plate, wherein along the first direction, a projection of the second layer of capacitors at least partially overlaps a projection of the first layer of capacitors. The capacitor density per unit area is improved by a three-dimensional stacking structure, thereby improving the power integrity of the power supply system.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

This invention relates to a method for manufacturing a printed circuit board with embedded vertical capacitors, comprising the following steps: drilling a first hole in a substrate to form a first hole; metallizing the hole wall of the first hole to form a conductive via ring; filling the metallized first hole to flatten it; drilling a second hole in the filled area of ​​the first hole, the second drilling using at least two different drill bits to form a second hole for placing the capacitor and a cutting hole for cutting the conductive via ring, the cutting hole dividing the conductive via ring into at least two mutually insulated conductive arc segments; placing the capacitor vertically into the second hole; and electrically connecting the capacitor's terminal electrodes to the conductive arc segments and / or external circuitry. The advantages of this invention are improved integration, enhanced high-frequency performance and power integrity, increased system reliability, and reduced manufacturing costs.

The application provides an electromagnetic interference suppression system and method of a smart television, and relates to the technical field of smart television, and the system comprises a SoC main chip, a WiFi module and a multi-path power management circuit; the SoC main chip is built-in with an LVDS interface, and differential display signals are output at a 315MHz base frequency; the WiFi module works at a 2.4GHz frequency band; the multi-path power management circuit comprises a DCDC converter, an LDO stabilizer and a power switch circuit, and a first decoupling network and a second decoupling network are used to provide power supply for a core voltage input end of the SoC main chip and an analog modulator voltage input end respectively; the first decoupling network and the second decoupling network provide a low-impedance power supply path for the SoC main chip at the 315MHz base frequency to maintain signal integrity. The application realizes frequency avoidance and power integrity collaborative optimization, and low-cost and simple suppression of harmonic interference of a high-speed interface on the WiFi module.

The present disclosure relates to a semiconductor device and a method of forming the same, the semiconductor device comprising: a first semiconductor structure and a second semiconductor structure stacked along a first direction; and the first semiconductor structure and the second semiconductor structure are bonded back-to-back; the first semiconductor structure comprises a first base and a first interconnection layer arranged along the first direction; the second semiconductor structure comprises a second base and a second interconnection layer arranged along the first direction; wherein a deep trench capacitor is formed in the second base; a plurality of heat dissipation channels are formed in the first base towards the second base; and / or a heat dissipation channel is formed in the second base towards the first base, on the one hand, the heat dissipation channels optimize the heat dissipation of the semiconductor device; on the other hand, the semiconductor structure with the deep trench capacitor can also improve the signal integrity and power integrity of the semiconductor device.

This application provides a method for fabricating an adapter board and the adapter board itself. By obtaining the adapter board body and a capacitor, a mounting area is defined on the surface of the adapter board body, and the capacitor is mounted to this mounting area using a surface mount technology, thus obtaining an adapter board with integrated capacitors. This application overcomes the limitation of related technologies where adapter boards used for multilayer packaging are merely pure interconnect structures. By integrating capacitors on the adapter board, power supply noise and line voltage drop can be effectively suppressed, thereby improving power integrity and ultimately meeting the technical requirements for power integrity.

The invention relates to a packaging substrate, a manufacturing method thereof and a semiconductor packaging structure. The packaging substrate comprises a core layer, a first power supply layer, a second power supply layer and at least one first impedance adjusting structure. The core layer is provided with at least one first embedding cavity. The first power supply layer and the second power supply layer are respectively arranged on the upper and lower sides of the core layer. The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conducting layers and a plurality of second conducting layers which are alternately stacked at intervals in the first direction perpendicular to the core layer, and any adjacent first conducting layer and second conducting layer are insulated. Wherein the plurality of first conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer, and the plurality of second conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer. According to the invention, the impedance of the power supply network in the packaging substrate can be reduced, so that the power supply integrity of the packaging substrate is ensured and improved.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

This invention discloses a stacked packaging structure and method, including a molding compound layer. At least four layers of chips are stacked and mounted face-down within the molding compound layer. Through-holes are formed in the molding compound layer and metallized to form a solid or overlay metallized structure. A redistribution circuit structure is disposed on the molding compound layer and ball-mounted. This invention achieves vertical interconnection of multi-layer chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The solid metallized through-holes effectively improve power integrity and signal integrity, enhance read / write performance of storage products, increase I / O density and bandwidth, and reduce power consumption. The solid metallized through-holes can be stacked, further shortening line length and reducing package size. Simultaneous fabrication of the redistribution circuit structure on both sides greatly improves packaging efficiency. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration and increasing packaging density.

The invention relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip power management system, electronic equipment and a three-dimensional integrated chip power management method. The side wall annular power supply bus surrounds the side wall area of the chip stacking body to form a closed annular conductor; and a plurality of tap distribution units arranged on the side wall annular power supply bus, wherein the plurality of tap distribution units are used for electrically connecting the power supply network of each layer of chip in the chip stack to the side wall annular power supply bus. Therefore, the closed annular power supply conductor is constructed on the side wall of the three-dimensional integrated chip stacking body and is connected with the packaging shell in parallel, the decoupling capacitor is integrated, and segmented monitoring control is performed, so that the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient power network reliability and the like caused by traditional TSV longitudinal power supply in a high-density 3D IC are solved; and the power supply integrity and reliability of the three-dimensional integrated chip are improved, and the system life is prolonged.

The invention relates to a power management method and device, a chip, electronic equipment and a computer readable storage medium. A target power supply module supplies power to a plurality of functional modules in the same power supply domain. The method comprises the following steps: querying a first functional module of a current to-be-processed power-on and power-off request and a second functional module which is executing a power-on and power-off process; combining the second function module with one or more first function modules to obtain a plurality of candidate combinations; determining system influence data corresponding to each candidate combination, and selecting a target candidate combination of which the system influence data meets a preset condition; and starting a power-on and power-off process of the target first function module according to the target first function module contained in the target candidate combination. The power-on and power-off requests of the functional modules are managed in a unified manner, simultaneous power-on and power-off of the functional modules having great influence on the power domain can be avoided, the current change rate can be effectively reduced, and the effects of simplifying the power integrity design, reducing the voltage drop and optimizing the power consumption are achieved.

The invention provides a reset control method and device for a universal graphics processor and a chip, and relates to the technical field of integrated circuits. The method takes over a reset control right by a reset management unit, and comprises the following steps: receiving a global reset signal for triggering reset initialization of a functional module of the universal graphics processor; dividing the function modules into a plurality of reset groups according to at least one grouping strategy in a power domain, a clock domain and a reset domain of the universal graphics processor; generating a group of reset control signals with different time sequences based on the reset group; and applying corresponding reset control signals to each reset group in sequence according to different time sequences. Through a staged and grouped reset control strategy, the transient current impact at the moment of reset is effectively inhibited, the problem of functional abnormality caused by power supply voltage drop in the reset process of the general graphic processor is solved, and the reliability of a chip and the integrity of a power supply are improved.

The invention discloses a layout power supply analysis method and device and a storage medium, and belongs to the technical field of semiconductors, and the method comprises the steps: extracting physical parameters of each device and parasitic resistance parameters of a power supply network from imported integrated circuit layout data; calculating a current source-to-ground current distribution value of each device according to the physical parameters, and converting a topological structure of the power supply network into a circuit connection relationship netlist comprising power supply nodes and grounding nodes; and in the circuit connection relation netlist, replacing each device with a corresponding current source-to-ground current distribution value, loading parasitic resistance parameters, generating a simulation netlist, inputting the simulation netlist into a simulator to execute direct current analysis, and obtaining actually measured impedance voltage drop data of each power supply node. According to the method, the physical parameters are directly extracted in the layout design stage, the current source-parasitic netlist is dynamically constructed, early-stage high-precision power supply integrity analysis can be achieved without waiting for LVS verification, and the problems of a traditional method in analysis efficiency and precision are effectively solved.

The application provides a flash memory stack package optimization method and device, equipment and a storage medium, and the method comprises the following steps: coupling simulation is performed on an initial three-dimensional package model of a flash memory stack, and a performance data set of the flash memory stack under a target workload is obtained; performance defects of the initial three-dimensional package model in terms of thermal management, power integrity and signal integrity are identified based on the performance data set, and package structure optimization parameters corresponding to each performance defect are generated respectively; and the package structure optimization parameters are integrated into the initial three-dimensional package model to obtain a target three-dimensional package model. Through coupling simulation on the initial three-dimensional package model, the performance data set is obtained, the package defects of the initial three-dimensional package model are identified based on the performance data set, and the corresponding package structure optimization parameter set is generated and integrated into the unified model, so that the accurate heat dissipation of the high heat flux density area can be improved, the impedance of the power distribution network can be effectively reduced, the crosstalk between high-speed signal paths can be suppressed, and the optimal balance of the overall performance can be achieved.

Test interconnect systems and methods are described. In one example, a test interconnect includes a housing structure that houses at least a portion of one or more compressible probes. The test interconnect also includes a plate that retains the one or more compressible probes relative to a load board, and a circuit board with one or more conductive planes that provide a conductive path for a supply voltage for a device under test. The circuit board is positioned on a side of the housing structure relative to a device under test that is opposite the load board side.

The present disclosure relates to a test method, device, electronic device, medium and product. The method comprises: disconnecting the connection between the storage controller and the interface of the storage chip, controlling the test module to be connected to the interface, and sending write test data to the storage chip via the interface for testing. Wherein, the data format of the write test data conforms to the data format of the interface, and the write test data is generated by the test module configuration. And receive the read data and perform verification to determine the test result. By using the test module to replace the storage controller, the test module can directly construct the required write test data, and send it to the storage chip through the interface between the storage controller and the storage chip, so that the sequence of the write test data is not affected by the scheduling strategy, to construct a more severe power integrity test scenario.

The invention relates to the field of driving, in particular to a sending end circuit driven by a current mode. Comprising a voltage bias circuit, a current bias circuit and a drive circuit. The voltage bias circuit is used for generating an amplitude-adjustable voltage VR2 by inputting a reference voltage Vref, and the amplitude of the amplitude-adjustable voltage VR2 is equal to that of the output voltage of the current mode driven transmitting end circuit; the current bias circuit is connected with the voltage bias circuit and is used for generating bias current, and the bias current generates proportional mirror current in the driving circuit; the drive circuit is used for being connected with the current bias circuit and used for receiving differential signals and outputting the differential signals. And the output stage provides precise bias current which is not influenced by the process, the power supply voltage and the temperature. And a low-voltage device is used as a switch tube to control output signal logic, so that the working speed of the driver is improved, and the damage of switch switching noise generated by using high-voltage digital logic to the integrity of a high-voltage domain power supply is also effectively avoided.

The invention relates to the technical field of multi-physics field coupling simulation, in particular to a power supply integrity simulation method based on multi-physics field coupling, which comprises the following steps of: performing accumulative correction on deviation nodes by adopting a residual network in the calculation process of the electromagnetic energy density and the temperature rise rate of a conductor layer; local power abnormal nodes are more easily highlighted in numerical value, the recognition capability of power supply network simulation on fine granularity deviation is remarkably enhanced, a plurality of energy correction sequences are constructed by adopting a Markov chain Monte Carlo method in a temperature and current residual judgment stage, and multi-field coupling solution presents more stable current distribution and temperature distribution in a steady-state stage. The prediction of the voltage fluctuation amplitude and the noise peak position is closer to the actual operation condition, and the high-risk node positioning, the power supply integrity evaluation credibility and the design parameter adjustment efficiency are synchronously improved by counting the high-deviation nodes on the basis of the steady-state response result and forming the multi-source coupling deviation feature set.

Land grid array (LGA) sockets with low-profile housings and stamped cylindrical pins are disclosed. Each pin includes a top contact portion, a bottom contact portion, and a serpentine spring portion that compresses along the vertical axis. In some embodiments, a bent electrically conductive strip provides a shorter electrical path to support high-speed data transmission. In other embodiments, the pin comprises a stub that contacts a pin hole plating layer to provide a shorter electrical path. The pins may be formed from beryllium copper and plated with palladium-gold. The socket housing, formed from printed circuit board laminate layers, defines cavities that receive and constrain the pins to limit movement and prevent damage. Localized ground and power structures, including plated-through holes and shielding vias, reduce crosstalk. The low-profile socket designs enhance signal and power integrity while enabling cost-effective manufacturability through progressive stamping and laminate-based assembly.

The invention discloses a power supply integrity repairing method and device and a storage medium, and belongs to the technical field of semiconductors, and the power supply integrity repairing method comprises the steps: obtaining layout power supply distribution network data, executing voltage drop analysis and electromigration analysis, and generating voltage drop distribution data and electromigration hotspot data; identifying an intersection region which conforms to the minimum punching rule and is associated with the voltage drop difference value and the electromigration value in the adjacent metal layers as a candidate punching region; for each candidate region, calculating the maximum number of through holes based on a voltage drop difference value when the region has no through hole, and calculating the maximum number of through holes based on an electromigration value when the region has the through hole; and executing a through hole adding operation according to a calculation result, and generating optimized layout data. The number of the through holes is dynamically determined through collaborative analysis of voltage drop and electromigration, the influence of parasitic parameters can be reduced while the integrity of the power supply is improved, the process reliability is ensured, the antenna effect is prevented, and comprehensive optimization of the power supply network is achieved.

The present application relates to the field of digital chip back-end power integrity analysis, and particularly relates to a worst transient IR-drop prediction method based on a multi-scale attention dense aggregation network. The present application is to solve the problem of high calculation cost of traditional commercial tools in voltage drop analysis, and the problem of insufficient accuracy caused by ignoring local current density and global power distribution network (PDN) topology constraints in existing machine learning models. The prediction method comprises: a multi-scale attention dense aggregation network architecture MADA-Unet is proposed, including key modules such as SC-MultiResBlock, DenseASPP, CTrans, etc. The method takes the chip layout static power consumption features and the transient power consumption map at multiple discrete time points as two-dimensional multi-channel input, extracts local anisotropic current density features through a multi-scale coding module containing horizontal and vertical separable convolution, models the global PDN topology constraint through a dense hollow spatial pyramid pooling module at the bottleneck layer, and uses a channel Transformer to adaptively aggregate heterogeneous features of different scales and different channels, and then outputs the worst transient IR-drop map and hot spot position by the decoder. The present application greatly reduces the operation amount and video memory consumption of the model while maintaining the high calculation efficiency of 2D convolution, and significantly shortens the chip sign kernel time.

The application relates to the technical field of high-speed electronic design automation simulation, and further relates to a via simulation method and system, a computer device and a storage medium. The method comprises the following steps: decomposing a multilayer via structure into multiple units, each unit comprising a cavity formed by a pair of plates and at least one via segment passing through the cavity; calculating an inter-plate impedance matrix of the cavity in each unit according to a finite element algorithm; calculating a coupling capacitance between the cavity and the via segment in each unit according to an analytical method; constructing multiple pi-type coupling circuit models according to the inter-plate impedance matrix and the coupling capacitance corresponding to each unit; cascading the pi-type coupling circuit models of each layer to obtain a multilayer via cascaded circuit model; and calculating scattering parameters according to the multilayer via cascaded circuit model. The method accurately and efficiently simulates a multilayer structure comprising vias, traces and an actual power ground plane, and realizes collaborative design of signal integrity and power integrity.

The invention relates to a method, a device and equipment for determining packaging parameters of a silicon substrate chip and a medium. The method comprises the following steps: acquiring current load data of a chip package and a first initial package parameter of a first conductive bump in the chip package, and determining a second initial package parameter of a second conductive bump in the chip package based on the current load data and the first initial package parameter, and matching the first initial arrangement area of the first conductive bump with the second initial arrangement area of the second conductive bump, and determining a first test packaging parameter of the first conductive bump and a second test packaging parameter of the second conductive bump according to a matching result. By adopting the method, the current load of the power supply network can be taken as a driving factor, the arrangement resource constraint of the first conductive bump in the chip package is combined, the arrangement area of the first conductive bump and the arrangement area of the second conductive bump are compared and analyzed through the two-dimensional arrangement area, the power integrity problem in the package is effectively controlled, and the reliability of the chip package is improved. And the thermal uniformity and the electrical stability are improved.

This invention discloses a semiconductor stacked packaging structure and method, including a molding compound I, which encapsulates at least two layers of chips. A molding compound II is disposed on the molding compound I, encapsulating at least two layers of chips. A through-hole (TVM) is formed on the molding compound II and metallized therein. Redistribution lines are fabricated on the molding compound II, and balls are placed on the redistribution lines. This invention achieves vertical interconnection of multiple layers of chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The TVM employs a solid metallization scheme, which can effectively improve the power integrity and signal integrity of the product, enhance the read / write performance of the storage product, increase I / O density and bandwidth, and reduce power consumption. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration, and increasing packaging density.

This invention discloses a semiconductor stacked packaging structure and its packaging method, including a molding compound I, which encapsulates at least four layers of chips. The molding compound I has through-holes (TVMs) and is metallized. Redistribution lines are also provided on the molding compound I, and balls are placed on the redistribution lines. This invention achieves vertical interconnection of multiple layers of chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The TMVs employ a solid metallization scheme, which can effectively improve the power integrity and signal integrity of the product, enhance the read / write performance of the storage product, increase I / O density and bandwidth, and reduce power consumption. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration, and improves packaging density.

The invention discloses a field-circuit coupling method and device based on a time domain hybrid finite element method and a delay insertion method. The method comprises the following steps: discretizing a three-dimensional electromagnetic structure through a tetrahedral mesh, reading the port characteristics of an IBIS model, constructing an electromagnetic field equation based on a hybrid finite element algorithm of tree-cotree decomposition, and reducing the order through a modal order reduction technology after discretization; an electromagnetic port is equivalent to a series structure, the series structure is coupled with an IBIS model equivalent circuit to construct an EM-IBIS system, and a circuit equation is solved through an LIM method; a self-adaptive local time step length strategy is adopted, an electromagnetic part adopts large-step-length propulsion, and a circuit part is subjected to self-adaptive subdivision iteration in each electromagnetic step length until a convergence condition is met. Simulation precision and efficiency are balanced, full-link simulation is supported, the design reliability of a high-speed and high-density electronic system can be improved, and the method has important application value in scenes such as signal integrity, power supply integrity and electromagnetic compatibility optimization.