92 results about "Power integrity" patented technology

The invention discloses a power supply integrity automatic test system based on multi-parameter intelligent cooperation, and belongs to the technical field of power supply test. Automatically identifying a power supply type through a power supply type identification and configuration module, and calling preset test parameters from a database to generate a test scheme; the method comprises the following steps: synchronously acquiring multi-modal data output by a power supply through a multi-parameter acquisition module, wherein the multi-modal data comprises test parameters of various power supplies; performing standardized scoring on each test parameter of the power supply through an intelligent scoring module; constructing a three-dimensional incidence matrix through an automatic evaluation module, dynamically adjusting the weight of each graded test parameter, and calculating an evaluation index of the power supply integrity; feedback information is generated through a feedback module, and a visual report of the power supply integrity test is generated according to the visual template; through mutual cooperation of the modules, automation of power supply integrity testing is realized, manpower is saved, and evaluation objectivity is improved.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The present invention discloses a method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module, which realizes simulation analysis of power integrity and signal integrity of the microsystem module, provides simulation judgment criteria, and improves simulation accuracy. The method includes the steps of merging a silicon substrate and a tube shell and then performing a DC voltage drop simulation. The steps are as follows: importing the layout of the tube shell and the silicon substrate into simulation software and setting simulation parameters; adding a voltage source and a current source between the power pin and the ground pin of the chip, starting the simulation software to perform a DC voltage drop simulation and performing calculations to obtain a simulation result; judging whether the simulation result meets the requirements according to the simulation criteria, and if so, completing the simulation; if not, locating the items in the layout that do not meet the simulation criteria, and modifying the layout of the items that do not meet the simulation criteria until the requirements are met and the simulation is completed.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention discloses a defense control system and method, a storage medium, electronic equipment and a chip, and relates to the technical field of chips, the defense control system comprises a defense judgment unit, a defense control unit and a load, and the defense control unit is connected with the defense judgment unit and the load; the defense judgment unit is used for performing power supply integrity defense risk assessment on the load according to the load characteristic information corresponding to the load and the power supply fluctuation information, and generating a defense control signal according to an assessment result; and the defense control unit is used for performing defense control on the load based on the defense control signal. Compared with the prior art, active defense can be adopted for the load, the problem of power supply abrupt change further caused under the condition that the load abrupt change occurs is avoided, the functional problem is further avoided, and the safety performance of the load can be improved.

The invention provides a joint simulation method, system and equipment for power supply integrity and signal integrity. The joint simulation method comprises the following steps: acquiring a first excitation signal; the first excitation signal is obtained by a first simulation result obtained by performing power supply integrity simulation on the to-be-tested system according to the second excitation signal; and performing signal integrity simulation on the to-be-tested system according to the first excitation signal and the second excitation signal to generate a second simulation result. According to the invention, by using the result of the power supply integrity simulation as the input of the signal integrity simulation, the power supply dynamic state of the circuit in the actual working environment can be simulated more accurately, and the influence of the power supply noise on the signal quality can be revealed, so that the potential problem can be avoided in the design stage. In addition, the problem of excessive design caused by separate simulation of SI simulation and PI simulation can be avoided, so that a better solution is provided for PPA and cost of a high-speed interface system.

The invention relates to a power supply integrity test method and device for a silicon substrate, and the method and device are applied to an upper computer in a test device connected with a to-be-tested silicon substrate, and the method comprises the steps: carrying out the failure behavior detection of the to-be-tested silicon substrate, and carrying out the detection of the failure behavior of the to-be-tested silicon substrate under the condition that the to-be-tested silicon substrate does not have the failure behavior; acquiring test data information acquired by a plurality of sensors arranged in the to-be-tested silicon substrate through a preset acquisition channel; wherein a plurality of sensors are arranged in different preset areas of the to-be-tested silicon substrate, and each sensor is used for feeding back acquired test data information of the position of the sensor to the upper computer; and determining a target area without errors in each area of the to-be-tested silicon substrate based on the test data information, and executing a reliability test on the target area to obtain an internal state test result of the to-be-tested silicon substrate. According to the invention, an accurate test result of the internal state of the silicon substrate can be obtained.

The present invention is directed to a method for verifying the integrity and authenticity of a printed circuit board, including associated components and packaging. The method is based on analyzing the power integrity of the power distribution network of the printed circuit board by measuring the S-parameter for the printed circuit board. Any tampering or counterfeiting can be determined by comparison of the S-parameter data or signature to a known authentic signature.

The invention discloses a direct current simulation method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining a structured data template file filled by a user, and enabling the structured data template file to define a topological structure and simulation parameters of a power network; analyzing the structured data template file, and extracting simulation configuration data; obtaining design data of the target printed circuit board; based on the simulation configuration data and the design data, topology verification and mapping are carried out, and a power supply tree is constructed; generating setting data required by direct current simulation based on the power supply tree; and calling a direct current simulation engine based on the setting data, and executing simulation calculation to obtain a simulation result. According to the embodiment of the invention, full automation of a direct current simulation process is realized through data driving, manual setting errors are thoroughly avoided, the efficiency of power supply integrity analysis is greatly improved, and the consistency from design input to verification output is ensured.

The invention relates to a chip verification method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring chip feature data and service data; constructing a power transmission model and a chip simulation model according to the chip feature data; calculating a power consumption curve based on the business data, and injecting the power consumption curve into the power supply transmission model for power supply integrity simulation to obtain power supply noise; the power supply noise comprises core power supply noise; using the core power supply noise to drive a clock source to obtain clock jitter; and injecting the power supply noise and the clock jitter into the chip simulation model for signal integrity simulation to obtain a simulation result. By adopting the method, the chip verification efficiency can be improved.

The invention provides a direct-current voltage drop calculation method, computer equipment and a storage medium. The method comprises the following steps: acquiring a design file of a PCB (Printed Circuit Board) and setting initial simulation parameters; performing spatial discretization processing on a metal layer of the PCB on a two-dimensional plane according to the geometric layout information to generate a grid composed of triangular units; enabling packaging nodes in the initial simulation parameters to correspond to grid nodes, and calculating a conductance value of an edge of each triangular unit when the edge is equivalent to a linear resistor; enabling a non-current source device which cannot be represented by linear admittance in the PCB to be equivalent to an external circuit, enabling the edge of the triangular unit to be equivalent to a linear resistor in the external circuit, and constructing a circuit network model; and constructing a linear equation set matrix according to the circuit network model, and solving the linear equation set matrix to obtain the DC voltage drop of the PCB. According to the scheme, the requirement for computing resources can be remarkably reduced, the computing speed is increased, the simulation precision is ensured, and an accurate direct-current voltage drop computing result is provided for power supply integrity analysis.

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

A capacitor assembly and a power supply system are provided. The capacitor assembly comprises: a first carrier plate and a second carrier plate, which are arranged in a stacking manner along a first direction and are spaced apart from each other, and the first carrier plate is electrically connected with the second carrier plate; a first layer of capacitors, which are arranged on a side of the first carrier plate facing the second carrier plate and are electrically connected with the first carrier plate; and a second layer of capacitors, which are arranged on a side of the second carrier plate facing away from the first carrier plate and are electrically connected with the second carrier plate, wherein along the first direction, a projection of the second layer of capacitors at least partially overlaps a projection of the first layer of capacitors. The capacitor density per unit area is improved by a three-dimensional stacking structure, thereby improving the power integrity of the power supply system.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

The invention relates to the technical field of circuit board processing, and discloses a manufacturing method of a printed circuit board with an embedded passive device, which comprises the following steps of: preparing a combined structure body which comprises a temporary carrier and a printed circuit board outer layer pattern formed on the temporary carrier; combining the passive device body with the outer layer pattern in a specific area of the combined structure body by adopting an attaching mode to form a composite structure body containing the passive device; and overlapping the composite structural body containing the passive device, a film, a printed circuit board with an inner layer structure and a copper foil according to a preset sequence to form an overlapped assembly. According to the manufacturing method of the printed circuit board with the embedded passive device, impedance abrupt change caused by poor interlayer contact is effectively eliminated, the power supply integrity and the signal integrity are greatly improved, and the quick response requirement of a high-integration-level chip in a high-speed switching transient state can be met.

This invention relates to the field of chip packaging technology, specifically a multifunctional BGA packaging structure and method. It includes a substrate with a wafer on its front side, a first electrical connection structure on its back side, and several side pads on the sides of the substrate. Compared to existing technologies, designing the memory and controller with side pads and bonding them from these pads not only reduces the overall area but also allows for direct interconnection between the memory and controller components, improving the read / write speed and power integrity of the solid-state drive.

This invention relates to a method for manufacturing a printed circuit board with embedded vertical capacitors, comprising the following steps: drilling a first hole in a substrate to form a first hole; metallizing the hole wall of the first hole to form a conductive via ring; filling the metallized first hole to flatten it; drilling a second hole in the filled area of ​​the first hole, the second drilling using at least two different drill bits to form a second hole for placing the capacitor and a cutting hole for cutting the conductive via ring, the cutting hole dividing the conductive via ring into at least two mutually insulated conductive arc segments; placing the capacitor vertically into the second hole; and electrically connecting the capacitor's terminal electrodes to the conductive arc segments and / or external circuitry. The advantages of this invention are improved integration, enhanced high-frequency performance and power integrity, increased system reliability, and reduced manufacturing costs.

The application provides an electromagnetic interference suppression system and method of a smart television, and relates to the technical field of smart television, and the system comprises a SoC main chip, a WiFi module and a multi-path power management circuit; the SoC main chip is built-in with an LVDS interface, and differential display signals are output at a 315MHz base frequency; the WiFi module works at a 2.4GHz frequency band; the multi-path power management circuit comprises a DCDC converter, an LDO stabilizer and a power switch circuit, and a first decoupling network and a second decoupling network are used to provide power supply for a core voltage input end of the SoC main chip and an analog modulator voltage input end respectively; the first decoupling network and the second decoupling network provide a low-impedance power supply path for the SoC main chip at the 315MHz base frequency to maintain signal integrity. The application realizes frequency avoidance and power integrity collaborative optimization, and low-cost and simple suppression of harmonic interference of a high-speed interface on the WiFi module.

The present disclosure relates to a semiconductor device and a method of forming the same, the semiconductor device comprising: a first semiconductor structure and a second semiconductor structure stacked along a first direction; and the first semiconductor structure and the second semiconductor structure are bonded back-to-back; the first semiconductor structure comprises a first base and a first interconnection layer arranged along the first direction; the second semiconductor structure comprises a second base and a second interconnection layer arranged along the first direction; wherein a deep trench capacitor is formed in the second base; a plurality of heat dissipation channels are formed in the first base towards the second base; and / or a heat dissipation channel is formed in the second base towards the first base, on the one hand, the heat dissipation channels optimize the heat dissipation of the semiconductor device; on the other hand, the semiconductor structure with the deep trench capacitor can also improve the signal integrity and power integrity of the semiconductor device.

The invention discloses a target impedance determination method for power supply integrity analysis and electronic equipment, and the target impedance determination method comprises the steps: determining a clock frequency range of a chip, and selecting N clock frequencies in the clock frequency range, N being an integer greater than 1; under any clock frequency in the N clock frequencies, current waveforms of the chip in at least two working states are obtained to obtain N current waveforms, and the at least two working states comprise a full-load state and an idle state; generating a frequency spectrum based on each current waveform to generate N frequency spectrums; target impedance is determined according to a preset voltage change value and the N frequency spectrums, and the preset voltage change value is determined based on the voltage drop limiting range of the working voltage of the chip. Through the above mode, the target impedance can be accurately determined so as to prevent a chip designer from making over-design or under-design, reduce the chip design cost and improve the design success rate of the chip.

This application provides a method for fabricating an adapter board and the adapter board itself. By obtaining the adapter board body and a capacitor, a mounting area is defined on the surface of the adapter board body, and the capacitor is mounted to this mounting area using a surface mount technology, thus obtaining an adapter board with integrated capacitors. This application overcomes the limitation of related technologies where adapter boards used for multilayer packaging are merely pure interconnect structures. By integrating capacitors on the adapter board, power supply noise and line voltage drop can be effectively suppressed, thereby improving power integrity and ultimately meeting the technical requirements for power integrity.

The embodiment of the utility model provides a semiconductor packaging piece which comprises a first intermediary, a first semiconductor tube core on the first intermediary, a second intermediary on the first semiconductor tube core and a second semiconductor tube core on the second intermediary. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by a metal-to-metal bond and a dielectric-to-dielectric bond. The second semiconductor die may be bonded to the second interposer by a metal-to-metal bond and a dielectric-to-dielectric bond. Bonding mechanisms between the integrated circuit die and the interposer allow for a greater density of conductive features that electrically connect the integrated circuit die to the interposer. The interposer may reduce die-to-die routing distances between the integrated circuit dies, improving signal integrity, power integrity, and overall performance of the semiconductor package during operation.

The invention relates to a packaging substrate, a manufacturing method thereof and a semiconductor packaging structure. The packaging substrate comprises a core layer, a first power supply layer, a second power supply layer and at least one first impedance adjusting structure. The core layer is provided with at least one first embedding cavity. The first power supply layer and the second power supply layer are respectively arranged on the upper and lower sides of the core layer. The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conducting layers and a plurality of second conducting layers which are alternately stacked at intervals in the first direction perpendicular to the core layer, and any adjacent first conducting layer and second conducting layer are insulated. Wherein the plurality of first conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer, and the plurality of second conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer. According to the invention, the impedance of the power supply network in the packaging substrate can be reduced, so that the power supply integrity of the packaging substrate is ensured and improved.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

This invention discloses a stacked packaging structure and method, including a molding compound layer. At least four layers of chips are stacked and mounted face-down within the molding compound layer. Through-holes are formed in the molding compound layer and metallized to form a solid or overlay metallized structure. A redistribution circuit structure is disposed on the molding compound layer and ball-mounted. This invention achieves vertical interconnection of multi-layer chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The solid metallized through-holes effectively improve power integrity and signal integrity, enhance read / write performance of storage products, increase I / O density and bandwidth, and reduce power consumption. The solid metallized through-holes can be stacked, further shortening line length and reducing package size. Simultaneous fabrication of the redistribution circuit structure on both sides greatly improves packaging efficiency. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration and increasing packaging density.

The invention relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip power management system, electronic equipment and a three-dimensional integrated chip power management method. The side wall annular power supply bus surrounds the side wall area of the chip stacking body to form a closed annular conductor; and a plurality of tap distribution units arranged on the side wall annular power supply bus, wherein the plurality of tap distribution units are used for electrically connecting the power supply network of each layer of chip in the chip stack to the side wall annular power supply bus. Therefore, the closed annular power supply conductor is constructed on the side wall of the three-dimensional integrated chip stacking body and is connected with the packaging shell in parallel, the decoupling capacitor is integrated, and segmented monitoring control is performed, so that the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient power network reliability and the like caused by traditional TSV longitudinal power supply in a high-density 3D IC are solved; and the power supply integrity and reliability of the three-dimensional integrated chip are improved, and the system life is prolonged.

The invention relates to a power management method and device, a chip, electronic equipment and a computer readable storage medium. A target power supply module supplies power to a plurality of functional modules in the same power supply domain. The method comprises the following steps: querying a first functional module of a current to-be-processed power-on and power-off request and a second functional module which is executing a power-on and power-off process; combining the second function module with one or more first function modules to obtain a plurality of candidate combinations; determining system influence data corresponding to each candidate combination, and selecting a target candidate combination of which the system influence data meets a preset condition; and starting a power-on and power-off process of the target first function module according to the target first function module contained in the target candidate combination. The power-on and power-off requests of the functional modules are managed in a unified manner, simultaneous power-on and power-off of the functional modules having great influence on the power domain can be avoided, the current change rate can be effectively reduced, and the effects of simplifying the power integrity design, reducing the voltage drop and optimizing the power consumption are achieved.

The utility model relates to the technical field of semiconductor packaging, and specifically relates to a fan-out and stacked packaging system-level semiconductor packaging structure. Comprising a first chip, a second chip, a third chip, a copper column and a plastic package material, copper wires are arranged at the two ends of the copper column, on the basis of an existing technology, a new system-in-package structure is adopted to meet the requirements of a product for high integration level, low cost performance, heat dissipation and the like, and the integration level of the product is improved through fan-out and stacking technologies; meanwhile, through material optimization and structure optimization, the stress of the product is greatly reduced, the service life of the product is prolonged, and the reliability of the product is improved; according to the design, the processing cost of the original packaging technology can be reduced, and the processing efficiency of the product is improved, so that the technical problem that the existing heat dissipation and interconnection technology cannot meet the corresponding heat requirement, the power integrity requirement and the high-speed signal transmission requirement of the product along with the large-scale popularization of high power and high frequency is effectively solved.

The invention provides a reset control method and device for a universal graphics processor and a chip, and relates to the technical field of integrated circuits. The method takes over a reset control right by a reset management unit, and comprises the following steps: receiving a global reset signal for triggering reset initialization of a functional module of the universal graphics processor; dividing the function modules into a plurality of reset groups according to at least one grouping strategy in a power domain, a clock domain and a reset domain of the universal graphics processor; generating a group of reset control signals with different time sequences based on the reset group; and applying corresponding reset control signals to each reset group in sequence according to different time sequences. Through a staged and grouped reset control strategy, the transient current impact at the moment of reset is effectively inhibited, the problem of functional abnormality caused by power supply voltage drop in the reset process of the general graphic processor is solved, and the reliability of a chip and the integrity of a power supply are improved.

The invention discloses a layout power supply analysis method and device and a storage medium, and belongs to the technical field of semiconductors, and the method comprises the steps: extracting physical parameters of each device and parasitic resistance parameters of a power supply network from imported integrated circuit layout data; calculating a current source-to-ground current distribution value of each device according to the physical parameters, and converting a topological structure of the power supply network into a circuit connection relationship netlist comprising power supply nodes and grounding nodes; and in the circuit connection relation netlist, replacing each device with a corresponding current source-to-ground current distribution value, loading parasitic resistance parameters, generating a simulation netlist, inputting the simulation netlist into a simulator to execute direct current analysis, and obtaining actually measured impedance voltage drop data of each power supply node. According to the method, the physical parameters are directly extracted in the layout design stage, the current source-parasitic netlist is dynamically constructed, early-stage high-precision power supply integrity analysis can be achieved without waiting for LVS verification, and the problems of a traditional method in analysis efficiency and precision are effectively solved.