Hybrid mesh partition method with design of integrity of system-level packaging power supply

A technology of power integrity and system-level packaging, which is applied in computing, electrical digital data processing, and special data processing applications. Improve the design and the effect of fewer nodes

Inactive Publication Date: 2011-02-16
SHANGHAI JIAO TONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method uses T-shaped or ∏-shaped circuit units to perform equivalent planes, and has good versatility. The disadvantage is that the circuit network is too complex and the number of components is large, which makes the simulation time and memory usage are large.
[0004] Therefor

Method used

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  • Hybrid mesh partition method with design of integrity of system-level packaging power supply
  • Hybrid mesh partition method with design of integrity of system-level packaging power supply
  • Hybrid mesh partition method with design of integrity of system-level packaging power supply

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Experimental program
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Embodiment

[0040] Such as figure 1 As shown, the implementation steps of this embodiment include the following five steps.

[0041] 1. Convex partition preprocessing

[0042] Since the rectangular grid division technique in this embodiment is aimed at a convex polygonal structure, it is necessary to perform convex division processing on a power / ground plane with a given arbitrary shape in advance. The steps of convex division are as follows: first determine the concave point of any polygon, and then connect the concave point with the vertex falling into the special area corresponding to the point to eliminate the concave point, so as to divide the original polygon into two sub-polygons, and then recurse on the sub-polygons Using this method, until all the concave points are eliminated, several convex polygons are finally obtained. The time complexity of this method is O(n), where n is the number of vertices of the original polygon. If the power / ground plane to be modeled is originally...

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Abstract

The invention relates to a hybrid mesh partition method in the field of electronic technologies, in particular to the hybrid mesh partition method with the design of integrity of a system-level packaging power supply. The hybrid mesh partition method comprises the following steps: (1) decomposing an irregular power supply/ground plane into a series of convex polygons by utilizing convex partition treatment; (2) obtaining an optimal rectangular mesh based on the recursive partitioning technology of the rectangular mesh, setting auxiliary ports on sides of the rectangular mesh, and establishing the transfer impedance relationship among the ports; (3) adopting a triangular mesh to fill the remaining structure, and carrying out modeling of an equivalent circuit for the triangular mesh; (4) establishing the electrical relationship among the ports at an interface of the rectangular mesh and the triangular mesh; and (5) solving simultaneous overall equations. The hybrid mesh partition method has the advantages of a wide range of applications, few internal nodes, high analysis precision and efficiency and the like.

Description

technical field [0001] The invention relates to a hybrid grid division method in the field of electronic technology, in particular to a hybrid grid division method for system-in-package power integrity design. Background technique [0002] With the development of electronic packaging and integration technology, the system-in-package technology that has been widely concerned can integrate high-speed digital devices, RF / analog devices, MEMS devices, and optoelectronic devices into one package to realize complex system functions. Since various components and functional blocks work together in the system, power integrity issues are a prominent challenge in system-in-package design. For example, when the same power supply is used in the system-in-package to power digital circuits and RF / analog circuits, the power / ground plane will become the main source of noise coupling. Synchronous switching noise in digital circuits will cause voltage fluctuations in the power distribution n...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 刘春天毛军发唐旻
Owner SHANGHAI JIAO TONG UNIV
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