Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

34results about How to "Effective instruction" patented technology

Data processing apparatus and method for executing a stream of instructions out of order with respect to original program order

A data processing apparatus and method are provided for executing a stream of instructions out-of-order with respect to original program order. At least some of the instructions in the stream identify one or more architectural registers from a set of architectural registers. The apparatus comprises a plurality of out-of-order components configured to manage execution of a first subset of instructions out-of-order, the plurality of out-of-order components being configured to remove false dependencies between instructions in the first subset. The plurality of out-of-order components include a first issue queue into which the instructions in the first subset are buffered prior to execution. A second issue queue is used to buffer a second subset of instructions prior to execution, the second subset of instructions being constrained to execute in order. Issue control circuitry is configured to reference both issue queues in order to determine an order of execution of instructions, and is configured to constrain the order of execution of the first subset of instructions by true dependencies between the instructions in both the first and second issue queues, and to constrain the order of execution of the second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues. This approach provides improved performance and/or reduced energy consumption.
Owner:RGT UNIV OF MICHIGAN

A data processing apparatus and method for executing a stream of instructions out of order with respect to original program order

A data processing apparatus and method are provided for executing a stream of instructions out-of-order with respect to original program order. At least some of the instructions in the stream identify one or more architectural registers from a set of architectural registers. The apparatus comprises a plurality of out-of-order components configured to manage execution of a first subset of instructions out-of-order, the plurality of out-of-order components being configured to remove false dependencies between instructions in the first subset. The plurality of out-of-order components include a first issue queue into which the instructions in the first subset are buffered prior to execution. A second issue queue is used to buffer a second subset of instructions prior to execution, the second subset of instructions being constrained to execute in order. Issue control circuitry is configured to reference both issue queues in order to determine an order of execution of instructions, and is configured to constrain the order of execution of the first subset of instructions by true dependencies between the instructions in both the first and second issue queues, and to constrain the order of execution of the second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues. This approach provides improved performance and/or reduced energy consumption.
Owner:THE RGT OF THE UNIV OF MICHIGAN

Information processing device

The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.
Owner:TAGO SHIN ICHIRO +7
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products