Information processing device

Abstract

The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.

Description

BACKGROUND OF THE INVENTION [0001] 1. Filed of the Invention [0002] The present invention relates to an information processing device which reads instructions, buffers and executes instructions by pipeline processing, and more particularly, to an information processing device which can reduce pipeline branching confusion when executing instruction sequences comprising branching instructions. [0003] The present invention further relates to a memory bus access system for an information processing device which performs instruction fetching, instruction buffering and instruction decoding and execution by pipeline processing, and more particularly provides an efficient memory bus access system in a dual instruction fetch-type information processing system which performs parallel fetches for branching-generating side instruction sequence (referred to below as target side instruction sequence) and non-branching-generating side sequence (referred to below as sequential side instruction sequ...

AI Technical Summary

Benefits of technology

[0017] Therefore, the object of the present invention is to restrict the increase in the hardware for instruction buffers and the like and reduce the confusion in the pipeline processing due to consecutive branching instructions in an information processing device which reads an instruction before the aforementioned instruction is executed by pipeline processing.

[0018] A further object of the present invention is to provide a memory bus access system for an information processing device which reduces the number of superfluous memory bus accesses and makes more efficient instruction fetches possible.

[0022] In addition, when the branching instruction is in the first instruction sequence, since it is necessary to employ at least the first and second instruction buffers which store the first instruction sequence that is being processed and the second instruction sequence of the branch target, the hardware for instruction buffering portions which store the branch target instruction sequence can be reduced.

[0023] In addition, the branch target address information of the next branching instruction inside the first instruction sequence being processed and the branch target address information of the next branching instruction inside the second instruction are stored in the first and the second branch target address information buffer. For this reason, by processing the branching instruction, irrespective of whether the system is in the branching state or in the non-branching state, it is possible to read the branch target instruction sequence immediately by this stored branch target address information, and the confusion in the pipeline processing due to consecutive branching instructions can be reduced.

Problems solved by technology

However, when there is a branching instruction in the instruction sequence, the branch target instruction which has the possibility of being executed directly after this branching instruction becomes an instruction which does not follow in address from that branching instruction and the pipeline processing becomes confused, possibly reducing the efficiency of the information processing device.

This results in a disadvantageous increase in the hardware (instruction buffer) of the information processing device.

In addition, because in the information processing device according to the prior art it was necessary to decode branching instructions so as to generate branch target addresses in order to read branch target instruction sequences of the branching instructions, a large amount of processing time was required after reading the branching instruction until the branch target instruction corresponding to the aforementioned branching instruction was read, so that an instruction buffer for a plurality of instruction sequences could not be employed effectively.

However, when a main memory bus access which makes an instruction fetch from the main memory is performed frequently, the traffic on the memory bus increases.

An increase in traffic on the memory busses causes delays in accessing the memory bus.

In particular, it is undesirable that, in a stage before the branching instruction is executed, it takes a long time to fetch from the main memory instructions which have become necessary as a result of the execution of the branching instruction, due to the fact that target side or sequential side instructions which will probably not be executed are extracted from the main memory.

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