21results about "Electric/magnetic computing" patented technology

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.

The invention discloses a capacitance detection circuit, which belongs to the field of detection circuits and comprises a transimpedance amplifier, a capacitance device, a first switch and a second switch. The first end of the capacitor is connected with the first switch, the second end of the capacitor is connected with the second switch, and charges are stored for the capacitor through the voltage difference between the two switches; the first end of the capacitor is connected with the negative input end of the transimpedance amplifier through a first resistor, and the second end is connected with the positive input end of the transimpedance amplifier through a second resistor; charges on the capacitor device are transmitted to the two input ends of the trans-impedance amplifier through the first resistor and the second resistor respectively, and voltage is reflected at the output end of the trans-impedance amplifier. According to the invention, the capacitance value of the capacitor device is directly detected through the transimpedance amplifier without being influenced by a light environment, and whether the external capacitor device is normally connected to the transimpedance amplifier can be detected in any environment.

Input digital bits are split into a first part and a second part. Digital-to-analog converter (DAC) is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, where the fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. Crossbar array coupled with the DAC stores weights encoded as analog conductance on resistive memory devices, and is configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. Analog-to-digital converter (ADC) coupled with the crossbar array, is configured to digitize the analog computation output from the crossbar array.

The present disclosure relates to the technical field of integrated circuits, and particularly relates to an integrator and an electronic device, the integrator is used for integrating an input signal to obtain an integrated signal, wherein the integrator is further used for determining the size of a power supply during the integration according to the voltage of the input signal, wherein when the voltage of the input signal is greater than a preset reference voltage, a second power supply is selected; otherwise, a first power supply is selected, and the driving capability of the second power supply is higher than that of the first power supply. The integrator provided in the embodiment of the present disclosure can select the size of the power supply according to the amplitude of the input signal, when the voltage of the input signal is greater than the preset reference voltage, the first power supply is selected; otherwise, the second power supply is selected, thereby realizing on-demand power supply of the power supply, dynamically adjusting the working mode of the integrator according to the change of the input signal, and avoiding the limitation caused by the fixed power supply mode in the related art.

The invention relates to an arrangement for performing a vector-matrix multiplication by means of synaptic components, consisting of: - a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and - a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The invention also relates to a method for controlling the arrangement. The invention addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. This problem is solved in that the word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

A processing system, or component thereof, and methods of making and using thereof, the system or component comprising at least one semiconductor device for real number computation using real machine computer integrated circuits implementing matter amplification by stimulated emission computation(s) (MASEC).

Computing circuit (1), in particular an analog computing device (20), further in particular an analog-digital hybrid computing device (30), comprising an analog computing circuit (50), designed and configured to perform an analog arithmetic operation; and comprising a detection and compensation circuit (I) and a temporary analog storage circuit (Sample and Hold Circuit, SH), designed and configured to detect an offset computing voltage (V1a) in the analog computing circuit and to perform a calibration with respect to the offset computing voltage (V1a).

The invention particularly relates to a physical reservoir for a magnetic reservoir computing device. The physical reservoir includes a ferromagnetic film including a two-dimensional arrangement of point deformations. The point deformations are dimensioned to function as pinning sites of magnetic domains of the ferromagnetic film. The invention also relates to a magnetic reservoir computing device comprising such a physical reservoir, and methods of operating and manufacturing such a reservoir computing device. The proposed method results in a low power consumption physical reserve that is easy to manufacture.

To provide a square root circuit capable of generating a highly accurate output value by suppressing and reducing the influence of a base current error.SOLUTION: In the square root circuit, a translinear circuit is configured by the first transistor 1 to the fourth transistor 4 using NPN bipolar transistors, and the fifth transistor 5 to the seventh transistor 7 using NMOS transistors are provided so that a base current error of the first transistor 1 to the fourth transistor 4 does not directly appear in the output current IOUT, and even if there is a base current error, the output current IOUT accurately proportional to the square root of the input current IIN is obtained.SELECTED DRAWING: Figure 1

A Method for determining a locally increased a thermal resistance (R1, R2) of a defective area (A1, A2) of a connection layer (L) is described. The defective area comprises defective spots (S1, S2). In a first alternative, a thermal resistance (R1, R2) assigned to a defective area (A1, A2) is dependent on the distance (d1, d2) between the spots (S1, S2) of the defective area, wherein the thermal resistance assigned to a defective area (A1, A2) increases with decreasing distance (d1, d2) between the spots (S1, S2) of the defective area (A1, A2). In a second alternative, a thermal resistance (R1, R2) assigned to a defective area (A1, A2) is dependent on the aspect ratio of the defective area (A1, A2), wherein the thermal resistance (R1, R2) assigned to a defective area (A1, A2), increases with decreasing aspect ratio of width vs. height (w1, h1), in recumbent orientation (RO). The method can be carried out by an artificial neural network.

There is disclosed a processing crossbar semiconductor device for processing an input vector a weight tensor, to derive an output vector as processed version of the weight tensor, the weight tensor having a plurality of weights, the crossbar processing device being configured to process each input electric value of an array of input electric values representing the input vector, the processing crossbar semiconductor device comprising: a set of weighting elements (101) arranged according to element columns and elements rows, each weighting element corresponding to a weight of the weight tensor, wherein the set of weighting elements is partitioned among a plurality of blocks (102), the plurality of blocks (102) being arranged according to super columns (108) and super rows (106) in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immediately subsequent element columns; a plurality of block output buses, each being associated with, and connected to, a plurality of blocks in the respective super row without being connected to blocks associated with, and connected to other super row, each block output bus including a plurality of block output lines, wherein each block of the plurality of blocks is configured, when activated, to weight input electric values of the array of input electric values by corresponding weights of the weight tensor, to provide electric weighted values to the block output bus associated with the super row of which the block is part; and a plurality of analog accumulation elements, each electrically connected with a block output line, to thereby provide a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks in the super row associated with the block output line, to derive an array of accumulated weighted output values which form the output vector.

The present disclosure relates to multi-bit digital-to-analog converters and continuous-time sigma-delta modulators. A four-way signal generator circuit generates four 2 N -bit control signals in response to a sampling clock and a 2 N -bit thermometer-coded signal. A digital-to-analog converter circuit has 2 N -bit unit resistor elements, where each unit resistor element includes four switching circuits controlled by corresponding bits of the four 2 N -bit control signals. Outputs of the 2 N -bit unit resistor elements are summed to generate an analog output signal. The four-way signal generator circuit controls generation of the four 2 N -bit control signals so that all logic states of the bits of the four 2 N -bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal can be a feedback signal in a sigma-delta analog-to-digital converter circuit that includes a multi-bit quantization circuit that operates to quantize a filtered loop signal to generate a 2 N -bit thermometer-coded signal.

Systems and methods are disclosed for deep learning solutions with analog AI. Analog AI systems can outperform their digital counterparts in speed and energy efficiency since computations are conducted directly in memory and analog processors inherently support parallel operations. An analog AI system may comprise a DAC, a programming module, row / column switches, a crossbar array and an ADC. The DAC provides an analog signal to the row / column switches, which along with the programming module, select a phase of operation, i.e., a forward, backward, or update path. A crossbar array is a trainable neural network that operates in the analog domain and comprises a matrix of programmable resistors, e.g., memristor devices. The crossbar array couples an output in the analog domain to the ADC. The result is a digital output from the crossbar array processing architecture.

An integrator operating based on a variable current is provided. The integrator includes an operational amplifier, wherein the operational amplifier includes an amplifying stage circuit and a bias circuit. The amplifying stage circuit is configured to provide an amplification gain. The bias circuit is coupled to the amplifying stage circuit and is configured to control a bias condition of the amplifying stage circuit according to the variable current output from a variable current source. In a sampling phase of the integrator, the variable current source switches the variable current to a sampling current value. In an integration phase of the integrator, the variable current source switches the variable current to an integration current value. More particularly, the sampling current value is less than the integration current value.

The disclosure relates to an integrator circuit for a Sigma-Delta, ΣΔ, modulator, the integrator circuit comprising an integrator module comprising a differential amplifier, a sampling module comprising sampling capacitors and a reference module comprising first and second pluralities of reference capacitors connected between respective first and second lines and first and second pluralities of reference switches for connecting each of the reference capacitors to either a first reference terminal or a second reference terminal. In operation, the reference switches are switched according to a thermometrically coded quantizer signal.

An electronic circuit includes word lines; bit lines intersecting the word lines at a plurality of grid points; and resistive processing units located at the grid points. Baseline stochastic pulse input units are coupled to the word lines; differential stochastic pulse input units are coupled to the word lines; and bitline stochastic pulse input units are coupled to the bit lines. Control circuitry coupled to the pulse input units is configured to cause each of the baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from the base input data, and each of the bitline stochastic pulse input units to generate a bitline pulse train using bit line input data. Neural network weights can thus be stored in the resistive processing units.

A system is described that comprises a memory for storing data representative of at least one kernel, a plurality of spiking neuron circuits, and an input module for receiving spikes related to digital data. Each spike is relevant to a spiking neuron circuit and each spike has an associated spatial coordinate corresponding to a location in an input spike array. The system also comprises a packet collection module configured to collect spikes and to organize the collected relevant spikes in the packet based on the spatial coordinates of the spikes, and a convolutional neural processor configured to perform event-based convolution using memory and at least one of the transformed input spike array and the transformed kernel.

The invention is notably directed to a physical reservoir for a magnetic reservoir computing apparatus. The physical reservoir includes a ferromagnetic film, which comprises a two-dimensional arrangement of point deformations. The point deformations are dimensioned to act as pinning sites for magnetic domains of the ferromagnetic film. The invention further concerns a magnetic reservoir computing apparatus comprising such a physical reservoir, as well as methods of operating and fabricating such a reservoir computing apparatus. The proposed approach results in a low-power-consumption physical reservoir, which is easy to fabricate.

The invention relates to a method for determining a locally increased thermal resistance (R1, R2) of a defect region (A1, A2) of a connecting layer (L). The defect region includes defect points (S1, S2). In a first alternative, the thermal resistance (R1, R2) assigned to the defective region (A1, A2) depends on the distance (d1, d2) between the points (S1, S2) of the defective region, the thermal resistance assigned to the defective region (A1, A2) increasing as the distance (d1, d2) between the points (S1, S2) of the defective region (A1, A2) decreases. In a second alternative, the thermal resistance (R1, R2) assigned to the defective region (A1, A2) depends on the aspect ratio of the defective region (A1, A2), the thermal resistance (R1, R2) assigned to the defective region (A1, A2) increasing as the aspect ratio of the width to the height (w1, h1) decreases in the lateral orientation (RO). The method may be performed through an artificial neural network.