53results about "Electric/magnetic computing" patented technology

The invention discloses a mass spectrometer electrometer based on a capacitance integrator, and belongs to the technical field of electrometers. Comprising a capacitance integrator, the capacitance integrator is connected with a voltage holding circuit, the voltage holding circuit is connected with an acquisition control circuit and an amplification circuit, and the amplification circuit is connected with the acquisition control circuit; and the acquisition control circuit controls electric signals input into the capacitance integrator, the voltage holding circuit and the amplifying circuit through an I / V conversion control method, so that I / V conversion is completed. The capacitance integration is used for completing I / V conversion, the problem of high-resistance forbidding can be solved, meanwhile, compared with high-resistance conversion, the capacitance integration is adopted, the temperature stability of the electrometer is improved, and noise is reduced.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention discloses an anti-interference circuit and method for capacitance detection, and the circuit comprises a to-be-measured unit which is provided with a to-be-measured capacitor, a reference voltage and a common-mode voltage, the first end of the to-be-measured capacitor is selectively connected with the reference voltage and the common-mode voltage, and the second end of the to-be-measured capacitor is connected with a ground potential; the quantization unit is connected with the to-be-measured unit and the integration unit and is used for quantizing an integration capacitor in the integration unit; the integration unit comprises an integrator and an integration capacitor, and the input end of the integration unit is connected with the unit to be measured; the counting unit is connected with the output end of the integration unit; wherein the integrating capacitor comprises a first integrating capacitor and a second integrating capacitor, the first integrating capacitor and the second integrating capacitor are connected in parallel, and the quantization unit quantizes the first integrating capacitor and the second integrating capacitor respectively.

The invention discloses a difference calculation circuit, a memory device including the same, and an operation method of the memory device. The memory device may include a format conversion circuit configured to generate a plurality of differential weights based on a plurality of weights provided from an external device; a memory cell array configured to store a first input element provided from an external device and the plurality of differential weights; a quantization circuit configured to generate a plurality of scaling coefficients based on the plurality of differential weights; and an input element scaling circuit configured to provide a plurality of output elements to an external device based on the plurality of scaling coefficients, the plurality of output elements corresponding to a product of the first input element and each of the plurality of weights.

An electronic circuit comprising: a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive processing units disposed at the plurality of grid points. A plurality of baseline stochastic pulse input units are connected to the plurality of word lines; a plurality of differential stochastic pulse input units are connected to the plurality of word lines; and a plurality of bit line stochastic pulse input units are connected to the plurality of bit lines. A control circuit connected to the plurality of pulse input units is configured to cause each of the plurality of baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the plurality of differential stochastic pulse input units to generate a differential pulse train using differential input data defining a difference from the base input data, and each of the plurality of bit line stochastic pulse input units to generate a bit line pulse train using bit line input data. Thus, a plurality of neural network weights are stored in the plurality of resistive processing units.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

An embodiment of the present application provides a phase compensator and related methods. The phase compensator includes: a numerical control module, a first feedback servo module, a second feedback servo module, and an input module; the input module is configured to generate an error signal based on a measurement signal and a reference signal, and send the error signal to the numerical control module, the first feedback servo module, and the second feedback servo module; the first feedback servo module is configured to generate a first feedback signal based on the error signal and a bias signal sent by the numerical control module; the second feedback servo module is configured to generate a second feedback signal based on the error signal and a zero-pole adjustment signal sent by the numerical control module; the numerical control module is configured to adjust the measurement signal based on the first feedback signal and the second feedback signal to obtain an adjusted measurement signal. In the embodiment of the present application, the input module, the first feedback servo module, and the second feedback servo module can be controlled based on the numerical control module to realize the adjustment of the measurement signal and improve flexibility.

The integrator circuit includes an operational amplifier, a first capacitor coupled to an input of the operational amplifier, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor coupled in parallel with the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by the first switch.

Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.

Embodiments of the present disclosure provide an adjustable square circuit, an auto-adjustment method for a square circuit, and a control module. The square circuit includes: a square unit that outputs a first signal; a mirror square unit that outputs a second signal; a current adjustment module configured to receive a target control signal, generate a compensation current, the magnitude of the compensation current being related to the target control signal, and an output end of the current adjustment module is connected to an output end of the square unit or the mirror square unit to compensate for the difference between the first signal and the second signal; wherein the target control signal is generated by the control module based on the voltage difference collected by the voltage acquisition module; the voltage acquisition module is configured to collect the output voltage of the square unit and the output voltage of the mirror square unit; the control module is configured to obtain the voltage difference between the output ends of the square unit and the mirror square unit, and the voltage difference is used to obtain the target control signal. Embodiments of the present disclosure can improve circuit mismatch and expand the dynamic range.

Configurable sensor units and sensor apparatus are provided. A configurable sensor unit comprises a sensor device for generating an electrical signal, dependent on a stimulus sensed by the device, in a circuit, and a programmable non-volatile memory element operable in the circuit as a load resistor for the sensor device, whereby resistance of the load resistor depends on a programmed state of the memory element. The sensor unit has an output for providing an output signal dependent on the aforementioned electrical signal and programmed state. Sensor apparatus may comprise a plurality of these configurable sensor units. Such sensor apparatus may be configured to perform in-sensor compute operations for neural network architectures. Further sensor apparatus comprises a configurable sensor unit and a controller for programming the memory element of the sensor unit to a programmed state dependent on an operating requirement for the sensor unit.

The invention discloses a capacitance detection circuit, which belongs to the field of detection circuits and comprises a transimpedance amplifier, a capacitance device, a first switch and a second switch. The first end of the capacitor is connected with the first switch, the second end of the capacitor is connected with the second switch, and charges are stored for the capacitor through the voltage difference between the two switches; the first end of the capacitor is connected with the negative input end of the transimpedance amplifier through a first resistor, and the second end is connected with the positive input end of the transimpedance amplifier through a second resistor; charges on the capacitor device are transmitted to the two input ends of the trans-impedance amplifier through the first resistor and the second resistor respectively, and voltage is reflected at the output end of the trans-impedance amplifier. According to the invention, the capacitance value of the capacitor device is directly detected through the transimpedance amplifier without being influenced by a light environment, and whether the external capacitor device is normally connected to the transimpedance amplifier can be detected in any environment.

Input digital bits are split into a first part and a second part. Digital-to-analog converter (DAC) is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, where the fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. Crossbar array coupled with the DAC stores weights encoded as analog conductance on resistive memory devices, and is configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. Analog-to-digital converter (ADC) coupled with the crossbar array, is configured to digitize the analog computation output from the crossbar array.

The present disclosure relates to the technical field of integrated circuits, and particularly relates to an integrator and an electronic device, the integrator is used for integrating an input signal to obtain an integrated signal, wherein the integrator is further used for determining the size of a power supply during the integration according to the voltage of the input signal, wherein when the voltage of the input signal is greater than a preset reference voltage, a second power supply is selected; otherwise, a first power supply is selected, and the driving capability of the second power supply is higher than that of the first power supply. The integrator provided in the embodiment of the present disclosure can select the size of the power supply according to the amplitude of the input signal, when the voltage of the input signal is greater than the preset reference voltage, the first power supply is selected; otherwise, the second power supply is selected, thereby realizing on-demand power supply of the power supply, dynamically adjusting the working mode of the integrator according to the change of the input signal, and avoiding the limitation caused by the fixed power supply mode in the related art.

The present invention discloses a weight unit and a memory device. The weight unit includes: a first field-effect transistor and a first resistive memory element connected to the drain of the first field-effect transistor; a second field-effect transistor and a second resistive memory element connected to the drain of the second field-effect transistor, the drain of the first field-effect transistor being connected to the gate of the second field-effect transistor, and the drain of the second field-effect transistor being connected to the gate of the first field-effect transistor; a third field-effect transistor and a third resistive memory element connected to the drain of the third field-effect transistor; and a fourth field-effect transistor and a fourth resistive memory element connected to the drain of the fourth field-effect transistor, the drain of the third field-effect transistor being connected to the gate of the fourth field-effect transistor, and the drain of the fourth field-effect transistor being connected to the gate of the third field-effect transistor.

A configurable sensor unit and a sensor device are provided. A configurable sensor unit comprising: a sensor device for generating an electrical signal in an electrical circuit as a function of a stimulus sensed by the device; and a programmable non-volatile storage element operable in the circuit as a load resistor for the sensor device, whereby a resistance of the load resistor depends on a programming state of the storage element. The sensor unit has an output for providing an output signal dependent on the aforementioned electrical signal and the programming state. A sensor device may include a plurality of these configurable sensor units. Such a sensor device may be configured to perform in-sensor computing operations of a neural network architecture. Additional sensor devices include a configurable sensor unit and a controller for programming storage elements of the sensor unit to a programmed state in accordance with operating requirements of the sensor unit.

The invention relates to an arrangement for performing a vector-matrix multiplication by means of synaptic components, consisting of: - a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and - a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The invention also relates to a method for controlling the arrangement. The invention addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. This problem is solved in that the word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

Some embodiments of the invention may include an eddy current nondestructive evaluation device. The eddy current nondestructive evaluation device may include a rotating body; a motor coupled with the rotating body such that the motor rotates the rotating body; a permanent magnet coupled with the rotating body; a pickup coil coupled with the rotating body; and an integrator circuit electrically coupled with the pickup coil that integrates a voltage from the pickup coil to produce integrated voltage data.

Embodiments of the present disclosure provide an adjustable square circuit, a control method for the square circuit, and a control module. The square circuit includes: a square unit for outputting a first signal; a mirror square unit for outputting a second signal; a temperature sensor; a storage module; and a current adjustment module for receiving a target control signal, generating a compensation current, the magnitude of the compensation current being related to the target control signal, and an output end of the current adjustment module being connected to an output end of the square unit or the mirror square unit for compensating for the difference between the first signal and the second signal; wherein the target control signal is obtained by the control module through look-up in the storage module based on the current temperature. Embodiments of the present disclosure can improve circuit mismatch and expand the dynamic range.

A processing system, or component thereof, and methods of making and using thereof, the system or component comprising at least one semiconductor device for real number computation using real machine computer integrated circuits implementing matter amplification by stimulated emission computation(s) (MASEC).

Computing circuit (1), in particular an analog computing device (20), further in particular an analog-digital hybrid computing device (30), comprising an analog computing circuit (50), designed and configured to perform an analog arithmetic operation; and comprising a detection and compensation circuit (I) and a temporary analog storage circuit (Sample and Hold Circuit, SH), designed and configured to detect an offset computing voltage (V1a) in the analog computing circuit and to perform a calibration with respect to the offset computing voltage (V1a).

The invention particularly relates to a physical reservoir for a magnetic reservoir computing device. The physical reservoir includes a ferromagnetic film including a two-dimensional arrangement of point deformations. The point deformations are dimensioned to function as pinning sites of magnetic domains of the ferromagnetic film. The invention also relates to a magnetic reservoir computing device comprising such a physical reservoir, and methods of operating and manufacturing such a reservoir computing device. The proposed method results in a low power consumption physical reserve that is easy to manufacture.

To provide a square root circuit capable of generating a highly accurate output value by suppressing and reducing the influence of a base current error.SOLUTION: In the square root circuit, a translinear circuit is configured by the first transistor 1 to the fourth transistor 4 using NPN bipolar transistors, and the fifth transistor 5 to the seventh transistor 7 using NMOS transistors are provided so that a base current error of the first transistor 1 to the fourth transistor 4 does not directly appear in the output current IOUT, and even if there is a base current error, the output current IOUT accurately proportional to the square root of the input current IIN is obtained.SELECTED DRAWING: Figure 1

A calibratable squaring circuit and a root mean square detector. A squaring circuit (10) comprises: a squaring unit (41) for outputting a first signal; a mirror squaring unit (42) for outputting a second signal, wherein the second signal is a static current (IB); a first current mirror structure, for mirroring and replicating the first signal to output a third signal; a second current mirror structure for mirroring and replicating the second signal to output a fourth signal; and a trimming unit (15), configured to adjust the mirror replication ratio of the first current mirror structure or the second current mirror structure, so that the difference between a direct-current component at an output end of a first output unit (13) and a direct-current component at an output end of a second output unit (14) falls within a first range. The present invention can achieve calibration of mismatches between the two squaring units in the root mean square detector, involves a simple structure, and can also achieve calibration of temperature-induced mismatch variations.

A Method for determining a locally increased a thermal resistance (R1, R2) of a defective area (A1, A2) of a connection layer (L) is described. The defective area comprises defective spots (S1, S2). In a first alternative, a thermal resistance (R1, R2) assigned to a defective area (A1, A2) is dependent on the distance (d1, d2) between the spots (S1, S2) of the defective area, wherein the thermal resistance assigned to a defective area (A1, A2) increases with decreasing distance (d1, d2) between the spots (S1, S2) of the defective area (A1, A2). In a second alternative, a thermal resistance (R1, R2) assigned to a defective area (A1, A2) is dependent on the aspect ratio of the defective area (A1, A2), wherein the thermal resistance (R1, R2) assigned to a defective area (A1, A2), increases with decreasing aspect ratio of width vs. height (w1, h1), in recumbent orientation (RO). The method can be carried out by an artificial neural network.