Vector calculating device

A vector operation and vector technology, applied in the field of vector operation devices, can solve the problems of insufficient on-chip cache, limited inter-chip communication, and inflexible vector length, etc., to achieve the effects of improved execution performance, flexible vector length, and convenient use

Active Publication Date: 2017-07-28
CAMBRICON TECH CO LTD
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Problems solved by technology

[0007] The purpose of the present invention is to provide a vector computing device to solve the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility of supported vector lengths.

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  • Vector calculating device
  • Vector calculating device
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Embodiment approach

[0025] According to an embodiment of the present invention, the vector operation device further includes: an instruction cache unit, configured to store vector operation instructions to be executed. During the execution of the instruction, it is also cached in the instruction cache unit. After an instruction is executed, if the instruction is also the earliest instruction among the uncommitted instructions in the instruction cache unit, the instruction will be back submitted. Once submitted , the operation performed by this command will not undo the changes to the device status. In one implementation, the instruction cache unit may be a reorder cache.

[0026] According to an embodiment of the present invention, the vector operation device further includes: an instruction processing unit, configured to obtain a vector operation instruction from the instruction cache unit, process the vector operation instruction, and provide it to the vector operation unit. Among them, the in...

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Abstract

The invention provides a vector calculating device comprises a memory cell, a register unit and a vector operation unit. Vectors are stored in the memory cell, addresses stored by the vectors are stored in the register unit, and the vector operation unit obtains a vector address in the register unit in dependence on a vector operation instruction, and then obtains a corresponding vector in the memory cell in dependence on the vector address, and carries out vector operation in dependence on the obtained vector to obtain a vector operation result. According to the invention, vector data participating in calculation is temporarily stored in a scratchpad memory, data in different widths can be supported flexibly and effectively during the vector operation process, and the execution performance of tasks including a lot of vector calculations is improved.

Description

technical field [0001] The invention relates to a vector operation device, which is used for performing vector operations according to vector operation instructions, and can well solve the problem that more and more algorithms in the current computer field include a large number of vector operations. Background technique [0002] At present, more and more algorithms in the computer field involve vector operations. Taking artificial neural network algorithms as an example, various neural network algorithms contain a large number of vector operations. In the neural network, the operation expression of the output neuron is y=f(wx+b), where w is a matrix, x and b are vectors, and the process of calculating the output vector y is multiplying the matrix w by the vector x, adding vector b, and then perform an activation function operation on the obtained vector (that is, perform an activation function operation on each element in the vector). Therefore, vector operations have beco...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F9/30036G06F17/16G06F9/3013G06F9/35G06F9/3824G06F9/3001
Inventor 陈天石张潇刘少礼陈云霁
Owner CAMBRICON TECH CO LTD
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