Vector calculating device

Abstract

The invention provides a vector calculating device comprises a memory cell, a register unit and a vector operation unit. Vectors are stored in the memory cell, addresses stored by the vectors are stored in the register unit, and the vector operation unit obtains a vector address in the register unit in dependence on a vector operation instruction, and then obtains a corresponding vector in the memory cell in dependence on the vector address, and carries out vector operation in dependence on the obtained vector to obtain a vector operation result. According to the invention, vector data participating in calculation is temporarily stored in a scratchpad memory, data in different widths can be supported flexibly and effectively during the vector operation process, and the execution performance of tasks including a lot of vector calculations is improved.

Description

technical field [0001] The invention relates to a vector operation device, which is used for performing vector operations according to vector operation instructions, and can well solve the problem that more and more algorithms in the current computer field include a large number of vector operations. Background technique [0002] At present, more and more algorithms in the computer field involve vector operations. Taking artificial neural network algorithms as an example, various neural network algorithms contain a large number of vector operations. In the neural network, the operation expression of the output neuron is y=f(wx+b), where w is a matrix, x and b are vectors, and the process of calculating the output vector y is multiplying the matrix w by the vector x, adding vector b, and then perform an activation function operation on the obtained vector (that is, perform an activation function operation on each element in the vector). Therefore, vector operations have beco...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a vector computing device to solve the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility of supported vector lengths.

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