Calculation method executed in quick flash memory fast and not caused abnormal power breakdown as well as its control system

Abstract

A quick algorithm preventing from irregular power cut off in flash memory and a control system is to mainly store logic BA and related interlock relationship mapping list information of PBA information in a PB paging of the memory protected by a set of ECC. When the host in operation, the controller logs in the mapping list information directly on a temporary memory of the said control device forits fetching, in which, the set up of mapping list is promptly and quickly without scanning program, and if the mapping list is wrong because of the irregular operation system then it will turn back to the last one to recover and ordinary interlock.

Description

Technical field [0001] The invention relates to an algorithm and a control system thereof that are fast and can prevent abnormal power outage in a flash memory. Background technique [0002] With the rapid development of the information industry, affected by the increasing speed of CPUs and the rise of IA products, high-speed data storage devices (memory) will also play an extremely important corner package. Among various data storage devices, flash memory is widely expected by users due to its non-volatile and easy to modify data access characteristics. [0003] Press like Figure 1A Shown is a schematic diagram of the structure of a general data storage system; at least one data storage device (such as Smart Media memory card, Memory Stick memory card and other flash memories) 11-19 is mainly connected to a computer through a control device 20 The host 29 is connected (of course, the control device 20 can also be built in a subsystem of the computer host 29), the control device...

AI Technical Summary

Problems solved by technology

However, if a clean block (such as B m+1 ) has completed the process of data transfer and filling in the logical address data value, but wants to change block B 2 When the erasing action has not been completed, abnormal shutdown conditions such as sudden power failure or crash occur, and when the microprocessor 25 restarts and scans the logic address data program of each physical block of each memory 11 again, it will be possible There are two data blocks B 2 and B m+1 All registered logical block address value is L 1 And point to the same corresponding search list 255 address (as shown by the dotted double arrow), or some blocks may not be connected, which will not only easily cause wrong connection of data, but even cause data damage

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