Matrix calculating device

Abstract

The invention provides a matrix calculating device comprising a memory cell, a register unit and a matrix operation unit. Matrixes are stored in the memory cell, addresses stored by the matrixes are stored in the register unit, and the matrix operation unit obtains a matrix address in the register unit in dependence on a matrix operation instruction, and then obtains a corresponding matrix in the memory cell in dependence on the matrix address, and carries out matrix operation in dependence on the obtained matrix to obtain a matrix operation result. According to the invention, matrix data participating in calculation is temporarily stored in a scratchpad memory, data in different widths can be supported flexibly and effectively during the matrix operation process, and the execution performance of tasks including a lot of matrix calculations is improved.

Description

technical field [0001] The invention relates to a matrix operation device, which is used for performing matrix operations according to matrix operation instructions, and can well solve the problem that more and more algorithms in the current computer field include a large number of matrix operations. Background technique [0002] At present, more and more algorithms in the computer field involve matrix operations. Taking artificial neural network algorithms as an example, various neural network algorithms contain a large number of matrix operations. In the neural network, the operation expression of the output neuron is y=f(wx+b), where w is a matrix, x and b are matrices, and the process of calculating the output matrix y is to multiply the matrix w by the matrix x, and add Matrix b, and then perform an activation function operation on the obtained matrix (that is, perform an activation function operation on each element in the matrix). Therefore, matrix operation has beco...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a matrix operation device to solve the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility of supported matrix lengths.

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