542results about "Single machine energy consumption reduction" patented technology

An air conditioning cooling apparatus and method which includes the steps of supplying cooling air generated from a cooling apparatus into an air passageway formed below a floor; guiding the cooling air within the air passageway into an equipment assembly disposed on the floor through an opening located in the floor; communicating the cooling air introduced into the equipment assembly into a plenum and introducing the air released from within the equipment into the plenum and communicating the released air through the cooling apparatus for cooling the released air. The method permits temperature differential between the air supplied to the air passageway and the air introduced into the plenum from the equipment assembly to be 45.degree. F. to substantially 40.degree. F. so as to reduce the power necessary for operating on the fan of the blowing apparatus. The equipment assembly utilizes an air flow control mechanism so as to substantially evenly distribute cooling air to the equipment.

Described is a system and method for monitoring a mobile computing Arrangement. The arrangement may include a sensor and a processor. The sensor detects first data of an event including a directional orientation and a motion of the arrangement. The processor compares the first data to second data to determine if at least one predetermined procedure is to be executed. The second data may include a predetermined threshold range of changes in the directional orientation and the motion. If the predetermined procedure is to be executed, the processor selects the predetermined procedure which corresponds to the event as a function of the first data. Subsequently, the predetermined procedures is executed.

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

This abstract has been included pursuant to Section 1.72(b) of the Rules for Patent and Trademark Cases, Title 37 of the Code of Federal Regulations. This abstract is intended only to enable the Patent and Trademark Office and the public to generally determine the nature of the technical disclosure. This abstract is not intended to aid in the interpretation of the scope of any claim. A portable computing device includes a keyboard controller that receives keystroke information as well as inputs from a graphical pointing device and conveys these to a main central processing unit. The keyboard controller additionally communicates with a battery module through a second interface in order to monitor and control the charging of the module. A low power secondary processor is interfaced to the keyboard controller through the second interface in order to receive keystroke information as well as information from the graphical pointing device. When the keyboard controller is instructed to do so, keystroke and graphical pointing information are conveyed exclusively to the secondary processor, thereby enabling the portable computing device to perform some functions without requiring the main central processing unit to be operational and thus operate in a low power mode.

A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Dynamically managing power consumption in a computer system having at least two parallel power converters in order to improve efficiency. A maximum power capacity for each of the power converters is determined and then power consumption of the computer system is monitored. If the power consumption of the computer system can be provided by less than all of the parallel power converters then one or more of the power converters is turned off, such that a reduced number of parallel power converters remains turned on. A reduced maximum power capacity of the reduced number of parallel power converters is determined and a power cap value is set for the computer system that is less than or equal to the reduced maximum power capacity. The computer system is throttled at the power cap to prevent power consumption of the computer system from exceeding the power cap value.

An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.

In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

A portable terminal having a cover that includes a transparent region and a display method thereof are provided. The display method includes displaying a UI element on an exposed display region in a state that the display region is covered by a cover, and controlling the display region that corresponds to the transparent region in response to a user input for selecting the UI element.

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

An apparatus and method for controlling an input power according to power management modes of a display device. In a saving mode of the power management modes, a power supply to the system is turned OFF according to an organic operation between components of the system. Thus, because the power supply to a power block within the system is turned OFF all, a consumed power is in a substantially zero state, comparable to a state in which a power plug is physically pulled out.

The object of the present invention is to provide an electronic device capable of reducing consumption of power supplied to active elements used for a rotary operation unit in a stand-by time.

The electronic device according to the present invention includes the rotary operation unit that is freely rotatable, active elements 31 and 32 for detecting rotation of the rotary operation unit, and control means 43 for controlling the power supply to the active elements 31 and 32 depending on a state of the device.

Provided is a low-power ZigBee device provided with a sleeping mode and an active mode including a power supplying unit for supplying a power; a Medium Access Control (MAC) processing unit for receiving a wake-up packet and for controlling a modem unit and an Radio Frequency (RF) unit; and a Central Processing Unit (CPU) for receiving and processing a data packet, wherein the MAC processing unit makes the power supplying unit apply a power to the CPU based on a result of checking an identification (ID) of the wake-up packet.

The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

An input device having a housing and electronic circuitry for detecting user inputs, and transmitting signals corresponding to those inputs to an electronic device, such as a computer. An antenna is provided for transmitting or receiving signals. A hand detection circuit is provided, which uses said antenna for detecting the proximity of a user's hand to the housing and producing a hand detect signal in response. In one embodiment, the antenna is a capacitive antenna. A capacitor is switched in parallel with the antenna when it is used in antenna mode, so that the impact on the antenna signaling of the capacitance of a user's hand is minimized. In one embodiment, a sleep mode is provided for the electronic circuitry to conserve power. The hand detect signal will awaken the input device from its sleep mode.

A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.

Provided is an information processing apparatus which includes a first-module including a first narrow-band communicator for performing narrow band communication with a second-module, a first broadband-communicator for performing broadband communication with the second-module, and a first controller for controlling an operation state of the first broadband-communicator according to an operation mode, and a second-module including a second narrow-band communicator for performing narrow-band communication with the first-module, a second broadband-communicator for performing broadband communication with the first-module, and a second controller for controlling an operation state of the second broadband-communicator according to an operation mode. The first controller places the first broadband-communicator in an operation state in a first mode, and places the first broadband-communicator in a standby state in a second mode. The second controller places the second broadband-communicator in an operation state in the first mode, and places the second broadband-communicator in a standby state in the second mode.

According to one embodiment of the invention, an approach is provided for determining alternative printing device arrangements. In general, the geographic locations, usage and costs of an existing set of printing devices are analyzed. A determination is made, based upon this analysis, whether one or more of the existing printing devices can be replaced by one or more replacement printing devices to provide an alternative printing device arrangement that has lower costs. The lower costs may reflect lower operational costs, lower energy costs, lower acquisition costs, or any combination of lower operational costs, lower energy costs and lower acquisition costs.

A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.

Embodiments of the present invention provide a method, system and computer program product for power optimization via virtualization opportunity determination. In an embodiment of the invention, a method for power optimization via virtualization opportunity determination can be provided. The method can include monitoring power utilization in individual server hosts in a cluster and determining a set of the server hosts in the cluster demonstrating low power utilization. The method also can include selecting a subset of server hosts in the set and migrating each VM in non-selected server hosts in the set to the subset of server hosts. Finally, the method can include powering down the non-selected server hosts.

The disk array device supplies appropriate power to various parts in accordance with the operating mode in cases where the output of the main power supply drops. The disk array device adjusts the power from a commercial power source 6 with an AC/DC power supply 5, and supplies this power to a power supply common bus 7. A disk drive group 1 and a control circuit board group 2 constituting electrical loads are respectively connected to the power supply common bus 7. When the supply of power from the main power supply stops, the capacitor box 3 supplies a relatively large current for a short time only, in order to retain data during an instantaneous power outage. Then, the battery boxes 4 supply power to the power supply common bus 7 for a relatively long period of time, in order to perform destage control and memory backup. The battery boxes 4 perform balancing control of the output current in order to suppress variation in the output current value among the battery boxes 4.