Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets

Abstract

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Description

RELATED APPLICATIONS[0001]This application is related to and claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 946,096, titled “AN INTERCONNECT IMPLEMENTING INTERNAL CONTROLS,” filed Jun. 25, 2007.NOTICE OF COPYRIGHT[0002]A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the software engine and its modules, as it appears in the Patent and Trademark Office Patent file or records, but otherwise reserves all copyright rights whatsoever.FIELD OF THE INVENTION[0003]Embodiments of the invention generally relate to an interconnect implementing internal controls. In an embodiment, configurable mapping of address regions onto one or more aggregate targets in an integrated circuit occurs.BACKGROUND OF THE INVENTION[0004]When an SOC has multiple DRAM interfaces for accessing multiple DRAMs in parallel at differing addresses, each DRAM ...

AI Technical Summary

Benefits of technology

[0007]A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect may maintain transaction path order to support outstanding transactions to multiple targets while maintaining transaction ordering; maintain request path order; maintain response path order; interleave channels in an aggregate target with unconstrained burst sizes; have configurable parameters for channels in an aggregate target and mapping of address regions onto the one o...

Problems solved by technology

This forced the software and system functional block to have to be aware of the organization and structure of the memory system when generating initiator requests.

In the traditional approach, the traffic may be split deeply in the memory subsystem in central routing units, which increases traffic and routing congestion, increases design and verification complexity, eliminates topology freedom, and increases latencies.

The created centralized point can act as a bandwidth choke point, a routing congestion point, and a cause of longer propagation path lengths that would lower achievable frequency and increase switching power consumption.

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