The application discloses a multi-layer stacked cluster computing
chip system capable of constrained expansion and an implementation method thereof, three-dimensional stacked
integrated circuit technology, adopts a central
radiation architecture, controls and manages multi-layer stacked units in a central control hub, realizes constrained expansion through
signal retiming compensation, and controls
transmission delay. Physical isolation composite
bus integrates data,
clock and power supply signals, and suppresses
crosstalk. The central integrated synchronization, routing and
power consumption control module dynamically optimizes
clock and scheduling efficiency; Manhattan shortest path is adopted for data forwarding to ensure
linear growth of computing power. The stacked unit is designed in a partition mode and reinforced with
through silicon via coupling defects, is adapted to multiple
CMOS processes, and meets the requirements of AI, high-
performance computing,
aerospace and edge scenarios. Compared with traditional chips, the computing
power density, energy efficiency and adaptability are improved, the attenuation in the expansion range is low, and the stability is enhanced.